Asymmetrical Multi-Core Memory Mapping for Network Devices
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Solution Overview
Problem
Conventional asymmetric processing dual-core systems require moving or copying large amounts of packet data, leading to inefficient bandwidth usage and increased power consumption.
Innovation Solution
The asymmetrical processing multi-core system employs a sub processing core that directly accesses memory using a memory absolute position, eliminating the need for data copying or moving, and incorporates a receiving end queue management module to process packets without transferring them to the user space.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If packet data is moved or copied between memory areas for processing by sub processing core, then processing collaboration between cores is achieved, but memory bandwidth is wasted and power consumption increases
Solution Approach 1:
The patent applies the copying principle in reverse - instead of copying data between memory areas, it enables the sub processing core to directly access the original packet data in the main processing core's memory area through memory mapping, eliminating redundant data copying while maintaining processing collaboration
Solution Approach 2:
The patent introduces a new dimension of memory access by enabling the sub processing core to access memory areas allocated to other processing cores through memory mapping mechanisms, transforming the traditional one-to-one memory access model into a many-to-one model that reduces data movement overhead
2Productivity
If packet data is moved or copied between memory areas for processing by sub processing core, then processing collaboration between cores is achieved, but memory bandwidth usage becomes inefficient
Solution Approach 1:
The patent eliminates unnecessary data copying by enabling direct memory access, where the sub processing core reads packet data directly from the main processing core's memory area through memory mapping, preserving memory bandwidth for actual data transmission rather than redundant copying operations
Solution Approach 2:
The patent makes memory areas universally accessible to multiple processing cores through memory mapping, allowing the same memory area to be accessed by both the main processing core for allocation and the sub processing core for processing, thereby eliminating the need for separate memory copies
3Productivity
If complete synchronization technique is implemented for asymmetric processing cores, then maximum network performance is attained, but system complexity increases
Solution Approach 1:
The patent enables the sub processing core to autonomously access and process packet data directly from the main processing core's memory area without requiring complex inter-core synchronization protocols, allowing each core to operate independently while maintaining collaboration through shared memory access
Solution Approach 2:
The patent extracts the synchronization requirement from the core collaboration mechanism by enabling direct memory access, separating the data access function from the processing coordination function and thereby reducing system complexity
Data Source
AI summary
An asymmetrical processing multi-core system used in a network device is provided. A sub processing core within the asymmetrical processing multi-core system facilitates a main processing core of the asymmetrical processing multi-core system in processing tasks, thereby improving an overall performance of the entire network device and causing the network device to operate more facilely. Different from a conventional processing method, the asymmetrical processing multi-core system does not require moving or copying a large amount of processed packet data, and thus a large amount of memory bandwidth is saved and the power consumption is reduced.