Asymmetrical Parallel-Combining RF Power Amplifier
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Solution Overview
Problem
CMOS RF power amplifiers face challenges with poor linearity, voltage and current stress reliability, and high power consumption, especially in achieving high efficiency and low distortion at power back-off conditions for WiFi standards like IEEE 802.11ac, which existing topologies like cascode, Doherty, and parallel-combining transformers struggle to address effectively.
Innovation Solution
The implementation of an asymmetrical Parallel-Combining (APC) Cascode topology power amplifier, which combines low-power and high-power amplifiers with dynamically controlled asymmetrical parallel-combining transformers, reducing current consumption and AM-AM/AM-PM distortions without requiring digital pre-distortion or tunable elements, and using static or dynamic biases for process, voltage, and temperature compensation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If switching mode power amplifiers or Doherty topology are used to achieve high PAE in deep PBO region, then power efficiency is improved, but complexity increases due to requiring DPD engine, phase shifters and programmable higher-Q resonant tank circuits
Solution Approach 1:
The power amplifier is segmented into a main PA and a auxiliary PA, each operating in different regions. The main PA handles high-power operations while the auxiliary PA supplements during deep power back-off conditions. This segmentation allows each amplifier to be optimized for its specific operating region, achieving high efficiency across the entire power range without requiring complex DPD engines or programmable resonant tank circuits.
2Manufacturing precision
If parallel-combining transformer (PCT), parallel-cascoded configuration (PCC) with active feedback linearizer, or multigate transistor (MGTR) techniques are used to improve linearity, then EVM performance is improved, but power consumption increases when achieving targeted EVM performance of -35 dB
Solution Approach 1:
The invention employs dynamic bias control where the bias voltages of the main PA and auxiliary PA are dynamically adjusted based on the operating conditions. This dynamic adjustment allows the amplifiers to maintain optimal linearity and efficiency at different power levels, achieving the targeted EVM performance without excessive power consumption that would result from static high-linearity configurations.
3Reliability
If cascode transistor configuration is used to reduce voltage stress over CMOS transistors, then reliability is improved, but current density in transistors increases
Solution Approach 1:
The power amplifier is segmented into a main PA and a auxiliary PA, each handling different power levels. This segmentation distributes the current load across two amplifier paths, reducing the current density in individual transistors while maintaining the voltage stress protection benefits of the cascode configuration. The auxiliary PA supplements the main PA during deep power back-off, further distributing the operational stress.
Data Source
AI summary
An integrated circuit RF power amplifier that includes a substrate; a low power (LP) amplifier; a high-power (HP) amplifier; and an asymmetrical parallel-combining transformer. The substrate is configured to supports the LP amplifier, the HP amplifier and the asymmetrical parallel-combining transformer. The LP amplifier is configured to amplify a LP RF input signal to provide a LP amplified signal. The HP amplifier is configured to amplify a HP RF input signal to provide a HP amplified signal. The HP amplified signal has maximal intensity that exceeds a maximal intensity of the LP amplified signal. The wherein the asymmetrical parallel-combining transformer may include (a) a HP primary winding that is constructed and arranged to receive the HP amplified signal; (b) LP primary windings that are constructed and arranged to receive the LP amplified signal; and (c) secondary windings that are magnetically coupled to the HP primary winding and to the LP primary windings, and are constructed and arranged to output a output signal.