Asymmetrical Precharge Programming for NAND Flash
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Solution Overview
Problem
Flash memory devices face program disturb issues due to insufficient biasing for preventing unselected memory cells from being inadvertently programmed, leading to performance degradation and operational inflexibility, especially when using sequential programming schemes that restrict random page programming.
Innovation Solution
A method for programming NAND flash memory that involves asymmetrically precharging channels to set selected memory cells to a program inhibit state, decoupling them from unselected cells, and applying a programming voltage only when necessary, using a source side asymmetrical precharge scheme to minimize program stress and allow random page programming.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If sequential programming schemes are used to prevent program disturb, then unselected memory cells are protected from inadvertent programming, but random page programming operations are prohibited resulting in performance degradation
Solution Approach 1:
The patent applies dynamics by making the programming scheme adaptable between sequential and random page programming modes. The biasing conditions and precharge voltages are dynamically adjusted based on the programming mode and unselected cell states, allowing the system to maintain program disturb prevention while enabling flexible random page programming operations.
Solution Approach 2:
The patent changes electrical parameters (biasing conditions, precharge voltages, pass voltages) to resolve the contradiction. By adjusting these parameters based on unselected cell states and programming mode, the system achieves both program disturb prevention and random page programming capability.
2Speed
If high voltages are applied to unselected wordlines during programming, then programming speed is improved, but unselected memory cells experience program disturb due to threshold voltage shifting
Solution Approach 1:
The patent applies local quality by differentiating the treatment of selected and unselected memory cells. Unselected cells receive reduced pass voltages and adjusted biasing conditions compared to selected cells, creating localized electrical conditions that prevent program disturb while allowing fast programming of selected cells.
Solution Approach 2:
The patent uses preliminary anti-action by precharging unselected cell channels to specific voltages before programming operations. This precharge state creates a protective condition that counteracts the harmful effects of programming voltages, preventing threshold voltage shifts in unselected cells.
3Reliability
If biasing for program inhibit state is increased to prevent unselected cells from being programmed, then program disturb is reduced, but device complexity and operational constraints increase
Solution Approach 1:
The patent segments the memory array into selected and unselected regions with distinct biasing conditions. By dividing the programming operation into separate voltage regimes for different cell groups, the system achieves effective program inhibit without requiring overly complex global biasing schemes.
Data Source
AI summary
A method for programming a NAND flash string. In the present method, wordlines are driven to a first pass voltage for coupling a string precharge voltage provided by a source line to the memory cells, where the string precharge voltage is greater than the first pass voltage. With the exception a first wordline corresponding to a first memory cell adjacent to a selected memory cell, all the other wordlines are driven to a second pass voltage greater than the first pass voltage. The first memory cell is positioned between the selected memory cell and a string select device. A second wordline corresponding to a second memory cell adjacent to the selected memory cell is driven to a first supply voltage for turning off the second memory cell. A third wordline corresponding to the selected memory cell is driven to a programming voltage greater than the second pass voltage. A bitline is then coupled to the selected memory cell.