Asymmetrical Source and Drain Transistors for RF Performance
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Solution Overview
Problem
In multi-gate field-effect transistors, the epitaxially-grown semiconductor material forming the source and drain can be underfilled, leading to degraded radiofrequency performance and increased contact resistance due to wide gate pitches, which limits the optimization of transistor operating characteristics.
Innovation Solution
A structure for a field-effect transistor is formed with a semiconductor body and a gate structure that includes an epitaxial semiconductor layer for one source/drain region and an ion-implanted region for the other, with the source/drain regions having asymmetrical widths due to varying gate pitches, allowing for independent engineering of source and drain properties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If epitaxial growth is used to form source and drain regions simultaneously, then manufacturing efficiency is improved, but the source and drain properties cannot be individually engineered to optimize transistor performance
Solution Approach 1:
The patent divides the source and drain formation process into separate sequential steps rather than simultaneous formation. First, a source region is formed using ion implantation, then a drain region is formed using epitaxial growth. This segmentation allows each region to be independently engineered with different properties while maintaining manufacturing efficiency.
Solution Approach 2:
The patent introduces dynamic flexibility by allowing different formation methods to be applied to source and drain regions based on specific design requirements. The asymmetric configuration enables the transistor to be optimized for particular applications by independently tailoring each region's characteristics.
2Adaptability or versatility
If wide gate pitches are used in multi-gate transistors, then device layout flexibility is improved, but epitaxial material underfilling occurs degrading radiofrequency performance
Solution Approach 1:
The patent employs asymmetric source and drain region widths to address the underfilling problem. By making the drain region wider than the source region, the structure compensates for the wide gate pitch geometry, ensuring complete epitaxial material filling while maintaining layout flexibility and improving radiofrequency performance metrics such as maximum stable gain.
3Ease of manufacture
If symmetrical source and drain regions are formed, then manufacturing simplicity is maintained, but optimal performance for specific design applications cannot be achieved
Solution Approach 1:
The patent applies local quality by creating asymmetric source and drain regions with different widths and formation methods tailored to specific functional requirements. The drain region is made wider and formed by epitaxial growth for better material quality, while the source region is formed by ion implantation, allowing each region to have optimized properties for its specific role in the transistor operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves radiofrequency performance by enhancing maximum stable gain, cut-off frequency, and breakdown voltage, while reducing gate-drain capacitance, thereby optimizing transistor performance for specific design applications.
Implementation Method 1
epitaxially grow sections of a semiconductor material from the semiconductor body to form the source and drain
Implementation Method 2
implant ions containing a p-type dopant or an n-type dopant into regions of the semiconductor body to provide the source and drain
Data Source
AI summary
Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. A gate structure extends over a semiconductor body, a first source/drain region includes an epitaxial semiconductor layer on a first portion of the semiconductor body, and a second source/drain region is positioned in a second portion of the semiconductor body. The gate structure includes a first sidewall and a second sidewall opposite the first sidewall, the first source/drain region is positioned adjacent to the first sidewall of the gate structure, and the second source/drain region is positioned adjacent to the second sidewall of the gate structure. The first source/drain region has a first width, and the second source/drain region has a second width that is greater than the first width.