Asymmetrical SRAM Cells Resolving Stability Trade-offs
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Solution Overview
Problem
Conventional SRAM cells face instability due to intrinsic device fluctuations and random mismatches as device dimensions are scaled, leading to degraded stability and limited improvement in static noise margin (SNM) in modern chip designs.
Innovation Solution
The implementation of asymmetrical SRAM cells with field effect transistors (FETS) having different oxide layer thicknesses, Germanium content, crystal orientations, and gate materials to adjust drive current and voltage characteristics, allowing for selective coupling to bit and word lines, enhancing read stability and write performance without increasing cell area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If device dimensions are scaled down to increase SRAM array area, then chip area utilization improves, but intrinsic device fluctuations and random mismatches increase causing stability degradation
Solution Approach 1:
The patent applies asymmetry by making the pull-down transistor (NFET) have a thicker oxide layer than the pull-up transistor (PFET), creating an asymmetrical inverter configuration. This asymmetry compensates for random mismatches and intrinsic device fluctuations in scaled devices, improving read stability without requiring larger device dimensions.
Solution Approach 2:
The patent changes the oxide layer thickness parameter of the NFET to be greater than that of the PFET. This parameter modification adjusts the drive current characteristics to achieve better noise margin and stability in scaled SRAM cells, directly addressing the reliability issue while maintaining small device dimensions.
2Ease of manufacture
If conventional symmetrical 6-T SRAM cell is used, then manufacturing simplicity is maintained, but static noise margin is limited and read stability degrades with scaling
Solution Approach 1:
The patent transforms the symmetrical 6-T SRAM cell into an asymmetrical configuration by modifying the oxide layer thickness of the NFET. This maintains the simple 6-transistor structure for ease of manufacture while significantly improving the static noise margin and read stability through the asymmetrical inverter design.
Solution Approach 2:
The patent applies local quality by selectively modifying only the NFET oxide layer thickness while keeping other device parameters similar. This localized change creates the necessary asymmetry to improve noise margin without complicating the overall cell structure or manufacturing process.
3Reliability
If NFET oxide layer is made thicker to reduce drive current, then read stability improves, but write capability may be affected
Solution Approach 1:
The patent carefully optimizes the NFET oxide layer thickness parameter to achieve the right balance. By selecting an appropriate thickness range, the design improves read stability through reduced drive current while maintaining sufficient write capability, resolving the trade-off between these two operational requirements.
Data Source
AI summary
Techniques are provided for asymmetrical SRAM cells which can be improved, for example, by providing one or more of improved read stability and improved write performance and margin. A first inverter and a second inverter are cross-coupled and configured for selective coupling to true and complementary bit lines under control of read and write word lines. The first inverter is formed by a first, n-type, FET (NFET) and a second, p-type, FET (PFET). Process and/or technology approaches can be employed to adjust the relative strength of the FETS to obtain, for example, read margin, write margin, and/or write performance improvements.