Asymmetrical Semiconductor Substrate Warpage Reduction
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Solution Overview
Problem
Conventional semiconductor substrates experience excessive warpage due to high volumes of conductive material on one side, leading to decreased yields and increased manufacturing costs, particularly in single level substrates which result in higher yield losses compared to multi-level substrates.
Innovation Solution
A single metal layer semiconductor substrate is created using buried pattern technology with asymmetrical glass fibers, where a conductive layer is patterned and embedded within a resin substrate, offset from the fibers to balance forces and reduce warpage, and the substrate is formed using a method involving pre-impregnated substrates with asymmetrical fibers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high volumes of conductive material are placed on one side of the substrate, then electrical functionality is achieved, but substrate warpage increases
Solution Approach 1:
The patent applies asymmetry by positioning the conductive material layer offset from the geometric center of the substrate, creating an asymmetric mass distribution that generates internal counterbalancing forces. This asymmetric placement compensates for the warpage-inducing effects of the conductive material volume, maintaining substrate flatness while preserving electrical functionality.
Solution Approach 2:
The patent changes the spatial parameter of the conductive material layer by offsetting its position from the substrate center. This parameter change (position offset) modifies the stress distribution within the substrate, reducing warpage while maintaining the necessary electrical properties of the conductive layer.
2Device complexity
If single level substrates are used to reduce complexity, then manufacturing complexity decreases, but yield losses increase due to warpage
Solution Approach 1:
The asymmetric offset of the conductive material layer in single-level substrates reduces warpage, thereby improving manufacturing yield without requiring complex multi-level structures. This asymmetric design enables single-level substrates to achieve performance previously only attainable with more complex multi-level architectures.
3Shape
If conductive material volume is reduced to minimize warpage, then substrate flatness improves, but electrical performance may deteriorate
Solution Approach 1:
The patent applies local quality by concentrating the conductive material in a specific offset region rather than distributing it uniformly. This localized placement maintains sufficient electrical performance in the functional areas while reducing the overall warpage-inducing volume effect, achieving both flatness and electrical reliability.
Data Source
AI summary
A semiconductor device includes a first carrier having a first resin disposed over the first carrier. A fabric is disposed over the first resin. A second resin is formed over the first resin and around the fabric to form an asymmetrical pre-impregnated (PPG) substrate. The first carrier is removed. A second carrier is provided and a first conductive layer is formed over the second carrier. A portion of the first conductive layer is removed. The first conductive layer is transferred from the second carrier to the first resin. The first conductive layer is oriented asymmetrically such that the first conductive layer is offset with respect to the fabric to minimize warpage. The second carrier is removed. A via is formed through the second resin and fabric to expose the first conductive layer. A second conductive layer formed in the via over the first conductive layer.