Asymmetrical Via Etch for Monolithic 3D Transistor Alignment
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Solution Overview
Problem
The challenge in monolithic 3D integration of ICs lies in achieving high positional accuracy for electrical interconnects between transistor terminals across multiple device levels, particularly due to the high aspect ratio of upper-level transistor structures, which can result in tapered via profiles and misalignment issues, leading to reduced IC yield.
Innovation Solution
An asymmetrical via etch process is employed, where the workpiece is oriented non-orthogonal to the reactive ion flux, allowing the lateral width of the via opening to increase significantly in one dimension parallel to the semiconductor sidewall, ensuring exposure of lower-level transistor terminals even with misalignment, while maintaining tight feature pitches in the other dimension.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a self-aligned via etch is performed using the upper-level transistor structure as a mask, then positional accuracy for interconnect alignment is improved, but the high aspect ratio of the upper-level transistor structure causes significant tapering of the via profile, resulting in reduced bottom via diameter and potential misalignment with lower-level transistor terminals
Solution Approach 1:
The patent applies asymmetry by introducing a sacrificial structure with a specific geometric profile (e.g., tapered or curved sidewalls) that is asymmetric relative to the upper-level transistor structure. This sacrificial structure is positioned between the upper and lower transistor structures, and when removed, it creates a via opening with a modified profile that compensates for the tapering effect, ensuring adequate bottom via diameter for reliable alignment with lower-level terminals.
Solution Approach 2:
The sacrificial structure serves as an intermediary element that mediates between the upper-level transistor structure (mask) and the lower-level transistor structure (target). By introducing this intermediate component with controlled geometry, the patent enables the via etch to achieve both self-alignment benefits and sufficient bottom opening size, resolving the contradiction between positional accuracy and alignment reliability.
2Productivity
If the lateral dimensions of transistor structures are minimized and structure density is maximized for a given technology node, then device performance and integration density are improved, but the positional accuracy requirement for interconnect alignment becomes exceedingly high
Solution Approach 1:
The asymmetric sacrificial structure compensates for the reduced tolerance margins caused by high integration density. By creating a via opening with expanded bottom dimensions through the sacrificial structure's geometry, the patent enables reliable alignment even when transistor structures have minimal lateral dimensions and high density, thus supporting continued scaling.
3Speed
If an anisotropic via etch is performed to achieve vertical etching directionality, then etching speed and aspect ratio capability are improved, but the via profile becomes significantly tapered with the bottom diameter being much smaller than the top diameter
Solution Approach 1:
The sacrificial structure acts as a geometric mediator that modifies the via profile during the anisotropic etching process. Its specific shape (e.g., tapered or curved walls) is designed to compensate for the inherent tapering of anisotropic etching, ensuring that the resulting via opening has adequate bottom dimensions while maintaining the benefits of vertical etching directionality and speed.
Solution Approach 2:
The patent changes the geometric parameters of the etching process by introducing the sacrificial structure with controlled dimensions and profile. This modifies the effective etching geometry, transforming the via profile from a simple tapered shape to one with compensated bottom dimensions, thereby addressing the shape issue while preserving etching speed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables a self-aligned, asymmetrical terminal interconnect that effectively connects upper and lower transistor terminals, reducing the risk of misalignment and improving IC yield by ensuring a sufficient bottom via dimension and reducing the tapered sidewall profile sensitivity.
Implementation Method 1
the workpiece is oriented non-orthogonal to the reactive ion flux, allowing the lateral width of the via opening to increase significantly in one dimension
Data Source
AI summary
One of a source, drain or gate terminal of an upper-level transistor structure is coupled to one of a source, drain or gate terminal of a lower-level transistor structure through an asymmetrical interconnect having a lateral width that increases within a dimension parallel to a semiconductor sidewall of the upper-level transistor by a greater amount than in an orthogonal dimension.