Asynchronous Arbiter Latch Array for Metastability-Resistant FSM Input
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Solution Overview
Problem
Asynchronous circuits face complexity and metastability issues when handling concurrent events due to the need for complex arbitration circuits, particularly in finite state machines, as mutex elements are prone to metastability effects when dealing with simultaneous or almost simultaneous requests from multiple communication channels.
Innovation Solution
An arbiter is designed to process multiple asynchronous data signals with associated request and acknowledge signals, using a latch array and logic circuitry to monitor request signals, generate a global request signal after a delay, and selectively activate acknowledge signals for active channels, allowing simultaneous processing of requests and reducing metastability effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If mutex elements are used to handle concurrent events in asynchronous circuits, then mutual exclusion between communication channels is achieved, but metastability effects occur when two events occur simultaneously or almost simultaneously
Solution Approach 1:
The patent applies preliminary action by triggering the latch array before the actual arbitration decision is needed. When a request signal becomes active, the latch array is triggered to capture the state of data signals and request signals, freezing them in a transparent state. This preliminary capture of signals before potential metastability issues arise allows the system to handle concurrent events reliably without suffering from metastability effects in the mutex elements.
2Reliability
If complex arbitration circuits are used to handle concurrent events in finite state machines, then proper arbitration of simultaneous requests is achieved, but circuit complexity increases significantly
Solution Approach 1:
The patent merges the functions of multiple arbitration operations into a single unified latch array structure. Instead of using separate complex arbitration circuits for each communication channel, the invention combines all request signals and data signals into a single latch array that is triggered simultaneously. This merging approach handles concurrent events from multiple channels in one step, significantly reducing circuit complexity while maintaining arbitration correctness.
Solution Approach 2:
The latch array serves multiple functions simultaneously: it acts as a trigger mechanism, a storage element for data signals, a capture device for request signals, and a synchronization point for the arbitration process. This multi-functionality eliminates the need for separate dedicated circuits for each arbitration task, reducing overall circuit complexity while ensuring proper handling of concurrent events.
3Reliability
If asynchronous control logic is added to implement handshake operations, then synchronization between circuit elements is achieved, but overhead in terms of circuit complexity increases
Solution Approach 1:
The patent applies self-service by designing the latch array to automatically trigger and capture signals based on the activation of request signals, without requiring external control logic. The latch array inherently performs the synchronization function by becoming transparent when triggered and capturing the state of signals, eliminating the need for additional asynchronous control logic to manage handshake operations between circuit elements.
Data Source
AI summary
An arbiter can be used for processing a plurality of asynchronous data signals. Each data signal is associated with a request signal and a respective acknowledge signal. The arbiter includes a latch array with an input coupled to receive the data signals and request signals and an output coupled to provide a data vector and a validity vector. The data vector includes values depending on the data signals and the validity vector includes values depending on the request signals when the latch array is in a transparent state. Logic circuitry is configured to trigger the latch array when any of the request signals becomes active, to activate a global request signal a delay time after the latch has been triggered, and to selectively activate the acknowledge signals for a channel or channels for which an active request signal has been latched.