Asynchronous Delta-Sigma Bitstream Recovery Without PLL or Clock Line
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Solution Overview
Problem
Existing analog-to-digital converter (ADC) systems require additional transmission paths for clock information, increasing layout complexity and requiring Manchester encoding, which complicates the recovery of non-encoded digital bitstreams without providing clock information.
Innovation Solution
The method employs asynchronous oversampling to calculate bit widths and determine an optimal oversampling factor using a minimization function, allowing accurate recovery of digital bitstreams without external clock information, reducing the need for additional transmission paths and eliminating the requirement for phase locked loop (PLL) circuitry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If additional transmission paths for clock information are provided, then accurate synchronization is achieved, but layout complexity increases
Solution Approach 1:
The patent extracts the clock information from separate transmission paths and embeds it within the data transmission path itself. The receiver extracts timing information from the incoming data stream by detecting transitions and measuring intervals between them, eliminating the need for separate clock transmission paths while maintaining synchronization accuracy
Solution Approach 2:
The single transmission line serves multiple functions: it transmits both data and clock information simultaneously. The data stream itself carries the timing information needed for synchronization, allowing one transmission path to fulfill the roles that previously required separate dedicated paths
2Reliability
If Manchester encoding is used, then clock information is embedded in the data stream, but the encoding complexity increases
Solution Approach 1:
Instead of encoding data with embedded clock transitions (Manchester encoding), the patent inverts the approach by using the natural transitions in the incoming data stream to derive clock information. The receiver measures intervals between transitions and uses these measurements to reconstruct timing information without requiring predetermined encoding schemes
Solution Approach 2:
The data stream serves itself by containing all necessary timing information within its own transition pattern. The receiver extracts clock information directly from the data stream's inherent transitions without requiring external encoding or additional signaling, allowing the system to be self-sufficient
3Reliability
If phase locked loop (PLL) circuitry is used, then clock synchronization is achieved, but the circuit complexity increases
Solution Approach 1:
The patent replaces the mechanical/electronic PLL synchronization system with a software-based or logic-based interval measurement approach. Instead of using phase detectors, voltage-controlled oscillators, and feedback loops, the system measures time intervals between transitions and calculates timing information through computational methods
Solution Approach 2:
The patent introduces an intermediary measurement mechanism that captures transition timestamps and uses these measurements to derive clock information. This intermediary layer of interval measurement and calculation replaces the direct PLL synchronization path, providing a simpler route to achieve the same synchronization goal
Data Source
AI summary
A method and circuit for recovering data from a digital bitstream received from an analog to digital converter includes asynchronously oversampling the digital bitstream at a sampling rate dictated by an estimate of a clock rate of the analog to digital converter and a nominal oversampling factor. The method and circuit also includes calculating widths of bits of the digital bitstream, and calculating a learned oversampling factor using the calculated widths of a predetermined number of bits of the digital bitstream and a minimization function. The method and circuit also includes calculating data bits to be inserted to a digital filter for digestion using the calculated widths of the bits of the digital bitstream and the learned oversampling factor.