Asynchronous Buffer Flip Mechanism for Graphics Processing
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Solution Overview
Problem
Conventional graphics processing methods, such as double- and triple-buffer procedures, require a callback mechanism that causes processors to wait, leading to inefficiencies and jamming, as they need to confirm the completion of drawing commands before proceeding.
Innovation Solution
Implementing asynchronous flush/flip commands that allow processors to send drawing commands without waiting for callbacks, using a first notice signal to confirm buffer completion and enable flipping, thereby avoiding the need for synchronous operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a callback mechanism is used to confirm drawing command completion before flipping the buffer, then the correctness of buffer flipping is ensured, but the processor must wait for the callback, causing time loss and processor jamming
Solution Approach 1:
The patent introduces a preliminary flag setting mechanism where the drawing engine sets a flag bit in the buffer control register before completing the drawing operation. This allows the processor to check the flag status immediately without waiting for a callback, thus resolving the contradiction by providing advance completion indication while maintaining reliability through proper flag management.
Solution Approach 2:
The patent introduces a buffer control register with flag bits as an intermediary between the drawing engine and the processor. This intermediary structure enables asynchronous communication where the drawing engine can signal completion through flag bits without requiring the processor to wait for callbacks, thus eliminating waiting time while ensuring correct buffer flipping through flag verification.
2Measurement precision
If synchronous flush commands are used to confirm drawing completion, then the accuracy of completion status is ensured, but the processor cannot send following commands until confirmation is received, reducing productivity
Solution Approach 1:
The patent enables continuous command sending by implementing asynchronous flush commands that use flag bit checking instead of synchronous waiting. The processor can continuously send drawing commands to the drawing engine while the engine independently manages buffer completion status through flag bits, ensuring both completion accuracy and continuous productivity without interruption.
Solution Approach 2:
The drawing engine performs self-service by automatically setting flag bits in the buffer control register to indicate completion status. This eliminates the need for the processor to poll or wait for completion confirmation, allowing the processor to maintain high productivity while the drawing engine autonomously tracks and reports its own completion status through the flag mechanism.
3Reliability
If the processor waits for callback mechanisms in double-buffer procedures, then the buffer state can be accurately confirmed, but the frame rate remains low at 10 fps
Solution Approach 1:
The patent implements preliminary flag setting by the drawing engine before buffer completion, allowing the processor to immediately check buffer state through flag bits without waiting for callbacks. This enables the processor to proceed with buffer flipping and send next commands without delay, increasing frame rate from 10 fps to 24 fps while maintaining reliable buffer state confirmation through flag verification.
Solution Approach 2:
The buffer control register with flag bits serves as an intermediary that enables high-speed asynchronous buffer state confirmation. The drawing engine sets flags to indicate buffer completion status, allowing the processor to quickly determine buffer readiness without waiting for callback mechanisms, thus achieving both reliable state confirmation and high frame rate performance.
4Manufacturing precision
If synchronous operations are used in triple-buffer procedures, then the buffer management accuracy is maintained, but the frame rate is limited to 20 fps
Solution Approach 1:
The patent enables continuous buffer management operations by implementing asynchronous flush commands with flag bit checking. The processor can continuously manage multiple buffers without synchronous waiting, sending drawing and flip commands across multiple buffers in sequence. This maintains precise buffer management through flag verification while achieving continuous operation that increases frame rate from 20 fps to 37 fps.
Solution Approach 2:
The drawing engine provides self-service by automatically managing buffer completion status through flag bits in the buffer control register. This eliminates the need for synchronous processor intervention to confirm completion, allowing the processor to maintain high-speed continuous buffer management across multiple buffers while the drawing engine autonomously ensures management accuracy through its own flag-setting mechanism.
Data Source
AI summary
A graphics processing method, which is applied to a plurality of buffers at least including a first buffer served as an on-screen buffer and a second buffer served as an on-drawing buffer, includes the steps of: sending a drawing command related to the second buffer to a drawing engine; when the drawing command related to the second buffer are received, drawing graphic data stored in the second buffer; sending an asynchronous flush command related to the second buffer to the drawing engine in order to confirm whether the drawing command related to the second buffer is completed; flushing the second buffer; and after the second buffer is flushed, sending a first notice signal to notify a display engine that the second buffer is capable of being flipped.