Asynchronous Buffer Data Flow Control for Variable Clock Domains
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Solution Overview
Problem
Memory controllers face challenges in efficiently transferring data across asynchronous buffers when processor frequency changes, leading to buffer overflow or underflow issues due to mismatched clock frequencies, which can introduce significant latency and affect performance.
Innovation Solution
A memory controller system with an asynchronous buffer that includes command control logic and data flow controller to manage data transfers by asserting move and launch signals, allowing for efficient data processing across clock frequency changes, thereby preventing buffer overflow and underflow.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the processor frequency is reduced to conserve power, then energy consumption is reduced, but buffer overflow occurs due to mismatched clock frequencies
Solution Approach 1:
The patent implements dynamic frequency adjustment in the asynchronous buffer, allowing the buffer's operating frequency to adapt to changes in processor frequency. This dynamic adjustment prevents buffer overflow when processor frequency is reduced while maintaining power-saving benefits, resolving the contradiction between energy efficiency and buffer reliability.
Solution Approach 2:
The patent employs feedback mechanisms that monitor the frequency relationship between processor and buffer, automatically adjusting buffer operation parameters in response to frequency changes. This feedback control ensures the buffer operates reliably across varying processor frequencies without overflowing, while preserving power-saving modes.
2Use of energy by moving object
If the processor frequency is reduced relative to memory frequency, then power consumption is reduced, but write buffer under run occurs due to invalid timing assumptions
Solution Approach 1:
The patent dynamically adjusts the write buffer's transfer timing based on actual processor frequency, replacing static timing assumptions with adaptive timing control. This allows the system to maintain reliable write buffer operation at reduced frequencies while preserving power-saving benefits.
Solution Approach 2:
The patent changes the timing parameters of write buffer operation based on processor frequency, adjusting transfer rates and timing intervals to match actual data arrival rates. This parameter adaptation prevents buffer under-run conditions while maintaining energy efficiency.
3Reliability
If write data is transferred to memory only after complete transfer into write buffer, then buffer under run is prevented, but significant latency is introduced
Solution Approach 1:
The patent initiates data transfer from write buffer to memory in advance, before the complete transfer into the buffer is finished. This preliminary action overlaps transfer operations, reducing total latency while maintaining buffer under-run prevention through frequency-adaptive timing control.
Solution Approach 2:
The patent enables continuous data flow by allowing memory transfer to begin while buffer filling is still in progress, eliminating idle waiting time. This continuous operation maintains reliability through frequency-adaptive control while minimizing latency loss.
4Manufacturing precision
If frequency changes are accommodated by waiting for complete data transfer, then timing accuracy is maintained, but system throughput is reduced
Solution Approach 1:
The patent implements dynamic frequency adjustment that allows timing parameters to adapt to processor frequency changes without requiring completion of data transfers. This dynamic timing control maintains accuracy while enabling overlapping operations that preserve system throughput.
Solution Approach 2:
The patent performs timing adjustments and frequency synchronization in advance, allowing subsequent data transfers to proceed without waiting for complete prior transfers. This preliminary synchronization maintains timing accuracy while improving overall throughput through reduced waiting time.
Data Source
AI summary
Embodiments of the present invention optimize data bandwidth across an asynchronous buffer in a system with a variable clock domain. A move signal may be asserted to transfer data associated with a command into the asynchronous buffer. After the data has been moved into the buffer, an acknowledge signal may indicate that the transfer is complete. A launch signal may transfer the data in the asynchronous buffer to memory. Embodiments of the present invention allow the processing of a next command to begin at the earliest possible time while data associated with a previous command is being transferred into and out of the buffer, thereby increasing throughput and improving performance.