Asynchronous Buffer Sampling for Serial Interface Underflow Detection
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Solution Overview
Problem
Conventional data transmission devices at serial interfaces face challenges in accurately detecting underflow errors due to asynchronous clock signals, leading to potential data transmission issues when data is not held in FIFO buffers.
Innovation Solution
A data transmission device is designed with a buffer synchronized with a first clock signal, utilizing a first and second determination circuit, flip-flops, and an output circuit to detect underflow errors by determining if data is held in the buffer, and transmitting this information as an interrupt signal using asynchronous communication sections operating on different clock edges.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If asynchronous clock signals are used for data transmission between master and slave, then data transfer flexibility is improved, but underflow error detection accuracy deteriorates
Solution Approach 1:
The patent introduces an intermediary detection mechanism that samples the FIFO buffer state at specific clock edges. The detection circuit acts as a mediator between the asynchronous internal clock domain and external clock domain, using synchronized sampling to accurately determine buffer underflow conditions despite the asynchronous nature of the clock signals.
Solution Approach 2:
The patent performs preliminary detection of the FIFO buffer state by sampling at the falling edge of the internal clock before the external clock's rising edge. This preliminary action ensures that the underflow condition is captured at the correct moment in the asynchronous timing sequence, allowing accurate error detection despite clock asynchrony.
2Speed
If data is transferred from FIFO to shift register asynchronously, then transmission speed is improved, but data integrity deteriorates due to underflow errors
Solution Approach 1:
The patent implements a feedback mechanism where the detection result of the FIFO buffer state is fed back to the data transmission control logic. This feedback allows the system to detect underflow conditions and prevent transmission of incomplete data, thereby maintaining data integrity while enabling asynchronous high-speed transmission.
Solution Approach 2:
The detection circuit serves as an intermediary between the asynchronous FIFO and shift register, monitoring the buffer state and providing control signals to prevent data integrity issues. This intermediary mechanism ensures reliable data transfer by blocking transmission when underflow conditions are detected, despite the asynchronous high-speed operation.
3Use of energy by moving object
If clock oscillation stops during non-transfer periods to save power, then energy consumption is reduced, but error detection capability deteriorates
Solution Approach 1:
The patent uses periodic action by enabling clock oscillation only during specific data transfer periods and allowing it to stop during non-transfer periods. The detection circuit is designed to capture the necessary buffer state information during the brief periods when the clock is active, enabling error detection capability to be maintained during transfer while achieving energy savings during idle periods.
Data Source
AI summary
A data transmission device of an embodiment includes a buffer, a first determination circuit, a first flip-flop, a second flip-flop, and a second determination circuit. The buffer holds input data of a predetermined bit width. The first determination circuit determines whether or not the input data is held in the buffer. The first flip-flop receives output of the first determination circuit as input and operates at one of a rising edge and a falling edge of a second clock signal which is asynchronous with the first clock signal. The second flip-flop receives output of the first flip-flop as input and operates at another of the rising edge and the falling edge of the second clock signal. The second determination circuit determines an error based on a request signal which is synchronized with the second clock signal and output of the second flip-flop.