Asynchronous Bundled-Data Interface for Timing Closure
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Modern digital ASIC designs face challenges in meeting timing constraints due to aggressive process and on-chip variations, leading to increased complexity and resource consumption, particularly in synchronous designs, prompting a shift towards asynchronous techniques like Bundled-Data circuits and Chronos Channels, which still require verification and may incur area and power overheads.
Innovation Solution
The implementation of a circuit with a bundled-data architecture and asynchronous compression/decompression circuits that serialize and deserialize data, providing a compression/decompression ratio, allowing for temporal compression and reduced hardware overhead, while maintaining compatibility with conventional EDA tools and simplifying timing constraints.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If synchronous design paradigm is used, then design simplicity is improved by ignoring wire and gate delays, but timing constraints become difficult to meet due to aggressive process and on-chip variations
Solution Approach 1:
The patent replaces the mechanical clock-synchronized timing system with an asynchronous handshake protocol system. Instead of relying on a global clock signal and fixed timing constraints, the design uses event-driven control where data transmission is triggered by request and acknowledge signals, eliminating the need to meet strict timing constraints while maintaining design simplicity.
2Reliability
If asynchronous techniques like Chronos Channels are used, then timing closure is improved by eliminating relative timing constraints, but area and power overheads increase due to synchronizers and quasi-delay-insensitive logic
Solution Approach 1:
The patent changes the operational parameters of the asynchronous interface by using single-rail logic with handshake protocols instead of multi-rail quasi-delay-insensitive logic. This parameter change reduces the hardware overhead while maintaining timing closure, as the simplified logic requires fewer transistors and less area compared to traditional asynchronous techniques.
Solution Approach 2:
The patent uses conventional latch or flip-flop based circuits that can be implemented using standard EDA tools, replacing the need for complex synchronizers and specialized asynchronous components. These conventional elements are more area-efficient and can be readily integrated into existing design flows without requiring expensive or area-intensive specialized hardware.
3Area of stationary object
If Bundled-Data circuits are used, then area and power savings are achieved by relaxing timing constraints and global signals distribution, but verification complexity increases due to reliance on relative timing constraints
Solution Approach 1:
The patent replaces the relative timing constraint-based verification system with an absolute event-driven verification system. Instead of verifying that data arrives within a relative time window, the verification ensures that request and acknowledge signals properly coordinate data transmission, simplifying the verification process while maintaining area and power efficiency.
4Reliability
If multiple clock islands or fully asynchronous techniques are adopted, then timing constraint satisfaction is improved, but design complexity and resource consumption increase
Solution Approach 1:
The patent creates a universal asynchronous interface that can work with both synchronous and asynchronous IP blocks through the bundled-data architecture with handshake protocols. This multi-functional interface eliminates the need for separate design methodologies for different clock domains, reducing design complexity while maintaining timing constraint satisfaction across the entire chip.
Data Source
AI summary
This application discloses the implementation of a self-timed IP with optional clock-less compression and decompression at the boundaries. It also discloses system and methods for application specific integrated circuits to convert RTL code and timing constraints to self-timed circuitry with optional clock-less compression and decompression at the boundaries.