Asynchronous Bus Synchronizer for Gated Clock Divider Updates
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Solution Overview
Problem
Synchronizing an asynchronous data bus with a control clock input in integrated circuits is challenging, especially when the control clock input is gated, and ensuring that the latest changes in the divider value take effect, particularly with multiple changes occurring in quick succession.
Innovation Solution
A data bus synchronizer comprising a cascade of registers that samples the asynchronous bus without an enable signal and generates a synchronized output in response to a load enable signal, which is triggered by a logic condition, ensuring that the latest stable value is always sampled and loaded onto the synchronized output.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the control clock input is gated to control IC operation, then power consumption is reduced, but the latest divider value changes may not be sampled correctly
Solution Approach 1:
The asynchronous sampling mechanism continuously captures divider values from the asynchronous bus before the clock is gated, storing them in registers. When the clock is ungated, the pre-computed load enable signal ensures the latest captured value is immediately loaded, resolving the contradiction by preparing data in advance during low-power states.
Solution Approach 2:
The patent introduces an intermediary sampling mechanism that operates independently of the gated control clock. This intermediary captures asynchronous bus values continuously and uses a load enable signal to transfer the latest value to the synchronized output when the clock is active, ensuring reliability without compromising power savings.
2Adaptability or versatility
If the system software changes the divider value frequently on the asynchronous bus, then clock frequency adaptability is improved, but synchronization complexity increases
Solution Approach 1:
The synchronizer uses self-service mechanisms where the asynchronous sampling registers automatically capture divider value changes without external control signals. The load enable logic autonomously determines when to transfer values based on change detection, enabling frequent software changes while maintaining simple synchronization through automatic change recognition.
Solution Approach 2:
The patent implements feedback through the load enable signal generation mechanism that monitors asynchronous bus changes. When a change is detected, the feedback loop triggers the load operation to update the synchronized output, allowing frequent divider value changes while maintaining synchronization through automatic change detection and response.
3Speed
If multiple divider value changes occur in quick succession, then response speed is improved, but the latest value may not be correctly captured
Solution Approach 1:
The asynchronous sampling registers continuously capture divider values in advance, creating a buffer of recent values. When multiple changes occur rapidly, the pre-captured values ensure that the latest change is already recorded and ready for transfer, maintaining both high response speed and accurate capture of the latest value.
Solution Approach 2:
The patent provides beforehand cushioning by maintaining multiple registered samples of the asynchronous bus value. This cushioning buffer ensures that even if multiple changes occur in quick succession, the system has pre-captured values available, guaranteeing that the latest value is captured accurately without missing any transitions.
Data Source
AI summary
A data bus synchronizer includes a plurality of registers arranged in a cascade, configured to generate a synchronized output in response to sampling an asynchronous bus without an enable signal, where the plurality of registers receive a value on the asynchronous bus. A last register of the plurality of registers is configured to generate the synchronized output in response to a load enable signal. The data bus synchronizer further includes a logic block configured to generate the load enable signal on satisfaction of a logic condition.