Asynchronous Channel Sampling With Oversampled ADC Timing Recovery
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Solution Overview
Problem
Existing data storage devices face challenges with synchronous sampling in data channels, which can lead to issues like clock slivering and instability in the timing loop, limiting flexibility in sample rates and increasing manufacturing costs and error rates.
Innovation Solution
Implementing an asynchronous sampling architecture using an oversampled analog-to-digital converter (ADC) with a digital timing loop that allows for flexible sample rates and improved timing recovery through a digital sample interpolator, which generates an oversampled digital signal at the baud rate of the channel circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If synchronous sampling is used in the data channel, then the timing loop can be simplified, but clock slivering and instability occur, limiting flexibility in sample rates and increasing error rates
Solution Approach 1:
The patent segments the sampling process by using multiple independent ADCs, each operating at different sample rates (e.g., 2x, 4x, 8x baud rate). This allows the system to flexibly select appropriate sample rates for different channel conditions without requiring a single synchronous sampling clock, thereby improving adaptability while maintaining reliability through redundancy and selection of optimal sampling rates.
2Ease of manufacture
If synchronous sampling with interpolated clock is used, then sample rate flexibility is reduced, but manufacturing costs increase due to clock slivering issues
Solution Approach 1:
The patent implements dynamic sample rate selection by providing multiple ADCs that can operate at different sample rates. The system can dynamically adjust which ADC and sample rate are used based on channel conditions, eliminating the need for fixed synchronous sampling clocks and their associated manufacturing complexities while maintaining full adaptability.
3Productivity
If synchronous sampling is used, then the timing loop becomes simpler, but latency in the timing loop increases, reducing performance
Solution Approach 1:
The patent performs preliminary sampling at multiple rates using parallel ADCs before the timing recovery process. By having multiple pre-sampled signals available at different rates, the timing loop can immediately select and process the most appropriate signal without waiting for clock synchronization, thereby reducing latency and improving overall performance.
Data Source
AI summary
Example channel circuits, data storage devices, and methods for asynchronous sampling from an oversampled analog-to-digital converter are described. The channel circuit may include an analog-to-digital converter configured to generate an oversampled digital signal from an analog data signal using a sample rate that is an integer multiple of the baud rate of the channel circuit. A digital sample interpolator may then interpolate interpolated digital signal values from multiple signal values of the oversampled digital signal and select values at baud rate to generate a baud rate digital signal. The baud rate digital signal may be used by an iterative detector in a timing loop and, once a target timing is achieved, for the iterative detector to detect data bits from the interpolated digital signal.