Asynchronous Circuit Data Synchronization via Triggered Frame Organization
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Solution Overview
Problem
Existing methods for collecting image data from integrated circuitry that operates asynchronously with respect to a camera trigger cannot synchronize the data to a known clock, making it difficult to analyze circuit performance over time.
Innovation Solution
A system and method that synchronizes data from asynchronously clocked circuitry by using a first clock signal and a synchronous trigger signal to collect high contrast data frames, determining a synchronization frame, and organizing them into a loop time sequence aligned with a synchronous clock, allowing for post-processing and realignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If data is collected from asynchronously clocked circuitry using a camera trigger, then time-resolved information can be captured, but the data cannot be synchronized to a known clock for analysis
Solution Approach 1:
The patent introduces an intermediary synchronization process that acts as a mediator between the asynchronous circuitry and the camera trigger. Detection events from the asynchronous circuit are timestamped and stored, then later correlated with camera frames through a synchronization algorithm. This intermediary layer allows time-resolved data to be captured while enabling subsequent synchronization to a known clock reference, resolving the contradiction between capturing time-resolved information and achieving clock synchronization.
2Reliability
If multiple data frames are collected at a higher rate than the clock signal, then sufficient data for synchronization is obtained, but data organization and processing complexity increases
Solution Approach 1:
The patent applies preliminary action by collecting and timestamping detection events at a high rate before the synchronization process is needed. Data frames are pre-collected with precise timing information, and a threshold-based filtering mechanism is pre-established to identify synchronization frames. This preliminary data collection and organization, performed before final synchronization analysis, allows for more reliable synchronization while managing complexity through structured pre-processing of the high-rate data stream.
Data Source
AI summary
A system and method are provided for synchronizing data collected from asynchronously clocked circuitry. The method provides an apparatus having inputs to accept a first clock signal and which has a plurality of devices synchronously timed to a third clock, but asynchronous from the first clock signal. Data frames are simultaneously collected for the plurality of devices, at a second clock repetition rate synchronous to the first clock, of device output detection events responsive to the trigger signal. The second clock repetition rate is greater than the first clock repetition rate. High contrast data frames are saved of device output detection events. A determination is made of a first device in the circuit block acting as the third clock trigger. Saved data frames with first device output detection events are recognized as synchronization frames, and the saved data frames are organized around the synchronization frames.