Asynchronous Circuit Self-Test via Dynamic Latch Switching
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Solution Overview
Problem
Asynchronous circuits used in cryptographic operations lack deterministic behavior, making it difficult to verify their integrity through traditional testing methods, as the output cannot be accurately predicted from given inputs, and thus require a mechanism to ensure they have not been compromised or manufactured with defects.
Innovation Solution
Incorporating a built-in self-test (BIST) component in the feedback path of the asynchronous circuit, which enables a change from non-deterministic to deterministic behavior during self-testing by using a master and slave latch configuration, allowing for comparison of output values with expected values to confirm integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional testing methods are used on asynchronous circuits, then the testing process is simple, but the output cannot be accurately predicted from given inputs due to non-deterministic behavior
Solution Approach 1:
The latch configuration dynamically switches between transparent mode during normal operation and capture mode during self-test, enabling the circuit to adapt its behavior based on operational phase. This dynamic switching allows deterministic capture of output values while maintaining non-deterministic operation during normal cryptographic functions.
Solution Approach 2:
The self-test mechanism periodically activates the latch capture function at specific intervals or conditions, allowing deterministic sampling of output values against expected values. This periodic capture action enables verification without continuously disrupting the non-deterministic operation of the asynchronous circuit.
2Reliability
If a BIST component is added to verify circuit integrity, then reliability is improved, but device complexity increases
Solution Approach 1:
The asynchronous circuit performs self-verification by comparing its own output values against expected values stored in the latch. The circuit serves its own testing function without requiring external testing equipment or complex verification systems, thereby improving reliability while minimizing additional complexity.
Solution Approach 2:
The latch component serves dual functions: storing expected output values during self-test mode and maintaining circuit state during normal operation. This multi-functionality allows integrity verification without requiring separate dedicated testing components, reducing overall device complexity.
3Measurement precision
If the latch is configured to capture output values for self-test, then measurement precision is improved, but the circuit operation is disrupted
Solution Approach 1:
The latch transparency is dynamically controlled based on operational mode. During normal cryptographic operation, the latch remains transparent allowing continuous data flow. During self-test phases, the latch transitions to capture mode to deterministically store output values for verification, then returns to transparent mode to resume normal operation.
Solution Approach 2:
The capture function is activated periodically or conditionally rather than continuously. The latch captures output values only at specific self-test intervals or under specific conditions, allowing the circuit to maintain continuous operation during normal phases while enabling verification when needed, thus minimizing disruption to productivity.
Data Source
AI summary
An indication of an operating mode of an asynchronous circuit may be received. A determination may be made as to whether the operating mode of the asynchronous circuit corresponds to a self-test of the asynchronous circuit. In response to determining that the operating mode of the asynchronous circuit corresponds to the self-test, a first clock signal may be provided to a first portion of a self-test component in a feedback path of the asynchronous circuit and a second clock signal may be provided to a second portion of the self-test component in the feedback path of the asynchronous circuit. Furthermore, a test value may be generated based on the first clock signal and the second clock signal.