Test Apparatus for Asynchronous Circuit Scan Testing
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Solution Overview
Problem
Asynchronous circuits lack a system clock, making it impossible to test them using scan-based methods, which are commonly employed in synchronous circuits for quality assurance and defect detection.
Innovation Solution
A test apparatus is designed with a D flip-flop and selectors to input and output test excitation signals on a pulse edge of a clock signal, allowing for the testing of asynchronous circuits by mimicking the scan-based testing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If scan-based testing is used for synchronous circuits, then testing quality and defect detection are improved, but asynchronous circuits cannot be tested because they lack a system clock
Solution Approach 1:
The patent introduces a scan clock signal as an intermediary element that bridges the gap between synchronous testing methodology and asynchronous circuit architecture. The scan clock, generated by a dedicated clock generation circuit, serves as a mediator that enables scan-based testing without interfering with the circuit's normal asynchronous operation. This intermediary clock signal allows test excitation signals to be serially transferred through the circuit for defect detection while maintaining the circuit's inherent asynchronous functionality.
2Ease of operation
If a clock signal is introduced for testing asynchronous circuits, then scan-based testing becomes possible, but the circuit architecture becomes more complex
Solution Approach 1:
The patent segments the clocking functionality by introducing a dedicated clock generation circuit that produces a scan clock signal specifically for testing purposes. This separate clock generation module operates independently from the circuit's normal operation, allowing scan-based testing to be performed without modifying the core asynchronous circuit architecture. The segmentation enables testability enhancement while minimizing impact on the original circuit design.
Solution Approach 2:
The patent implements dynamic control of the scan clock signal through a clock enable signal that activates the clock generation circuit only during testing modes. The clock generation circuit dynamically produces scan clock signals with adjustable frequencies and duty cycles, allowing flexible adaptation to different testing requirements. This dynamic approach enables scan-based testing functionality to be activated only when needed, reducing the impact on normal circuit operation and minimizing overall system complexity.
Data Source
AI summary
Disclosed are a test apparatus and a testable asynchronous circuit. The test apparatus includes: a first input end, a second input end, a third input end, a fourth input end, a fifth input end, a first selector, a second selector, a D flip-flop, and a first output end. The first input end is configured to input a data signal or a test result of a previous circuit under test; the second input end is configured to input a test excitation signal or a test result that is output by a previous test apparatus; the third input end is configured to input a clock signal; the fourth input end is configured to input a selection signal; and the fifth input end is configured to input a selection signal.