Asynchronous Circuit Timing Analysis via Duplicate Registration Pins
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Solution Overview
Problem
Current timing analysis tools are inadequate for optimizing asynchronous circuit designs, particularly due to the complexity introduced by multiple asynchronous clock domains and varying timing requirements across modules in system-on-chip (SoC) architectures, which complicates data transfer and synchronization, leading to inefficiencies in power consumption and reliability.
Innovation Solution
A computer-implemented method is introduced that involves creating a new timing cell library with duplicate pins for registration stages, allowing for timing analysis and optimization by modifying the circuit design to include duplicate pins for analysis purposes, and then reconnecting to produce an optimized production design, enabling effective timing analysis and optimization of asynchronous circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If asynchronous circuit designs are used to reduce clock circuitry and improve power efficiency, then power consumption is reduced and size is minimized, but timing analysis becomes significantly more complex and challenging
Solution Approach 1:
The patent creates duplicate timing pins (dummy pins) that copy the functionality of normal pins to establish analysis paths. These duplicate pins allow timing tools to trace signal paths through asynchronous circuits without requiring actual asynchronous operation, enabling conventional timing analysis methods to be applied to asynchronous designs.
Solution Approach 2:
The patent introduces duplicate timing pins as intermediary elements that mediate between the asynchronous circuit operation and conventional timing analysis tools. These intermediary pins provide a bridge that allows standard synchronous timing analysis methodologies to work with asynchronous circuit behavior.
2Adaptability or versatility
If multiple asynchronous clock domains are used in SoC architectures, then adaptability and flexibility are improved, but timing analysis and synchronization between domains become more difficult
Solution Approach 1:
The patent segments the timing analysis problem by creating separate analysis paths for each clock domain through duplicate pins. This allows each asynchronous domain to be analyzed independently while maintaining the ability to analyze cross-domain timing relationships, breaking down the complex multi-domain problem into manageable segments.
Solution Approach 2:
The patent adds a temporal dimension to the analysis by creating time-stamped duplicate pins that capture timing information at different moments in the asynchronous cycle. This allows timing relationships to be analyzed across multiple time dimensions rather than a single synchronous reference.
3Ease of operation
If conventional timing analysis tools are used on asynchronous circuits, then tool simplicity is maintained, but analysis accuracy and reliability are insufficient
Solution Approach 1:
The patent creates duplicate timing pins that copy the structural and functional characteristics of normal pins, allowing conventional timing tools to operate on asynchronous circuits without modification. The duplicate pins preserve the timing relationships needed for accurate analysis while maintaining compatibility with existing toolchains.
Solution Approach 2:
The patent changes the parameter representation by introducing duplicate pin identifiers and associated timing metadata that encode asynchronous timing behavior. This allows conventional tools that operate on standard pin parameters to accurately analyze asynchronous circuits by interpreting the transformed parameter set.
Data Source
AI summary
Methods and systems for timing analysis and optimization of asynchronous circuit designs are disclosed. Registration stages are placed between combinational logic circuits. For timing purposes, the registration stages are modified to have a duplicate set of pins. New paths are formed in the circuit for the purposes of timing analysis. The paths are analyzable by timing tools. Once the timing analysis is complete, the paths are reverted to original paths, and new devices are selected for the circuit design based on results of the timing analysis. An updated design is sent for manufacture, based on the timing analysis and optimization of the asynchronous circuit.