Asynchronous Circuit Timing via Sample-Based Counter Increment
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Solution Overview
Problem
Passing timing signals over asynchronous interfaces in electronic devices, such as those used in LTE communications, introduces uncertainty due to differing clock rates and lack of synchronization between circuit portions, affecting the accuracy of system time synchronization.
Innovation Solution
An electronic device with two asynchronous circuit portions, where the second circuit portion maintains timing by incrementing its counter based on sample arrival times, eliminating the need for dedicated synchronization signals and allowing accurate time-stamping without requiring synchronized clocks, using a predetermined increment value that accounts for the difference in clock frequencies and sample rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If timing signals are passed over asynchronous interfaces between circuit portions, then device complexity is reduced by eliminating dedicated synchronization signals, but measurement precision deteriorates due to uncertainty from differing clock rates
Solution Approach 1:
The patent introduces a timing signal that is transferred between circuit portions clocked by different clock signals, serving as an intermediary to establish timing relationships across asynchronous boundaries. This timing signal acts as a mediator that allows the second circuit portion to synchronize its counter with the first circuit portion without requiring the clock signals themselves to be synchronized, thus resolving the contradiction between reduced complexity and maintained precision.
2Adaptability or versatility
If different circuit portions use different clock frequencies, then adaptability is improved by allowing independent clocking, but reliability deteriorates due to timing uncertainty across the asynchronous interface
Solution Approach 1:
The patent changes the parameter of clock frequency independence by allowing the first and second clock signals to operate at different frequencies while maintaining reliable timing through the transfer of timing signals. The second circuit portion adjusts its counter based on received timing signals from the first circuit portion, enabling each circuit portion to use optimized clock frequencies for their specific functions while maintaining system-wide timing coherence.
Data Source
AI summary
An electronic device comprises a first circuit portion comprising one or more components, including a first counter, which are clocked by a first clock signal. The first circuit portion is arranged to receive a data stream comprising a plurality of data signals. A second circuit portion comprises one or more components clocked by a second clock signal and a second counter not clocked by the second clock signal. The first clock signal is not synchronised to the second clock signal. The second circuit portion is arranged to: receive samples of the data stream from the first circuit portion at a sample rate and to time-stamp each received sample with a count value of the second counter. The second circuit portion increments the count value of the second counter by a predetermined increment value for each received sample.