Asynchronous Clock Division for Multiphase SMPS Interleaving
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Solution Overview
Problem
Existing multiphase switch-mode power supply (SMPS) interleaving methods require phase locked loops (PLLs) or delay locked loops (DLLs) to achieve high switching frequencies, which consume significant power and silicon area, leaving no power budget for other components in the regulator.
Innovation Solution
The method employs asynchronous clock division to interleave multiple phases without using PLLs or DLLs, reducing power consumption and silicon area by using a dynamic clock divider and SET distribution logic block to control phase blocks with a common switching frequency and period.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If phase locked loops (PLLs) or delay locked loops (DLLs) are used to achieve high switching frequencies, then switching frequency is improved, but power consumption and silicon area increase significantly
Solution Approach 1:
The patent extracts and removes the PLL/DLL components from the multiphase SMPS system, replacing them with a simpler clock division approach. By taking out the power-consuming locked loop circuitry and substituting it with basic clock division logic, the system achieves high switching frequencies without the associated power penalty
Solution Approach 2:
Instead of using complex PLL/DLL circuits to generate phase-shifted clock signals, the patent inverts the approach by using a single high-frequency clock and dividing it down to generate the required phase-shifted signals. This reverse engineering approach eliminates the need for power-hungry locked loop circuitry
2Speed
If phase locked loops (PLLs) or delay locked loops (DLLs) are used to achieve high switching frequencies, then switching frequency is improved, but silicon area increases significantly
Solution Approach 1:
The patent extracts and removes the PLL/DLL components from the multiphase SMPS system, replacing them with a simpler clock division approach. By taking out the area-intensive locked loop circuitry and substituting it with basic clock division logic, the system achieves high switching frequencies without the associated silicon area penalty
Solution Approach 2:
The patent uses a single master clock signal and creates copies of this signal through simple division to generate the required phase-shifted clock signals for multiple phases. This copying approach using basic logic gates consumes minimal silicon area compared to implementing separate PLL/DLL circuits for each phase
3Use of energy by moving object
If traditional multiphase interleaving methods are used, then power consumption and silicon area are reduced, but control complexity and difficulty of detecting and measuring phase relationships increase
Solution Approach 1:
The patent incorporates feedback mechanisms that monitor the phase relationships and clock signals, automatically adjusting for any drift or timing errors. This feedback approach simplifies the control of phase relationships by using straightforward comparators and control logic rather than complex synchronization schemes
Solution Approach 2:
The patent uses a common high-frequency clock signal as the master reference for all phase blocks, ensuring that all phases operate from the same timing potential. This equipotential approach using a shared clock source simplifies phase relationship control by eliminating the need for complex inter-phase synchronization and measurement
Data Source
AI summary
In described examples, a phase interleaver obtains (i) a first signal indicating a variance between a reference voltage and a regulated output voltage and (ii) a second signal indicating a voltage across an energy storage device. A voltage regulator includes multiple phase blocks collectively configured to generate the regulated output voltage. In a repeating cycle, (i) the voltage across the energy storage device is increased while the second signal is less than the first signal and (ii) in response to a determination that the second signal is greater than the first signal, the energy storage device is substantially discharged, multiple stages of a clock divider are transitioned in the phase interleaver, and a set of control signals is output from the clock divider. The control signals have a common switching frequency and a common switching period. The control signals control the phase blocks active in generating the output voltage.