Asynchronous Clock Domain Timing Analysis via Equivalent Synchronous Models
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Solution Overview
Problem
Asynchronous clock domain crossings in electronic chip design lead to errors due to the lack of accurate timing analysis, as existing tools suppress analysis on signal paths with asynchronous clocks, requiring labor-intensive custom assertions and gate-level simulations, which are time-consuming and may result in inaccurately modeled designs.
Innovation Solution
The solution involves identifying and renaming clocks associated with signal paths across asynchronous clock domains, allowing for independent timing analysis based on specific timing specifications for each signal group, ensuring consistency between timing analysis and design verification, and making the RTL design portable across different implementations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If existing timing analysis tools suppress analysis on signal paths with asynchronous clocks, then tool complexity is reduced, but timing analysis accuracy deteriorates leading to design errors
Solution Approach 1:
The patent segments the asynchronous clock domain crossing analysis into multiple independent phases: (1) identifying the asynchronous crossing point, (2) determining equivalent synchronous timing specifications, (3) performing setup/hold analysis, and (4) executing timing verification. This segmentation allows the tool to handle asynchronous paths systematically without requiring complete suppression of analysis, thereby maintaining accuracy while managing complexity.
Solution Approach 2:
The patent introduces an intermediary transformation process that converts asynchronous timing analysis into equivalent synchronous timing analysis. By determining equivalent timing specifications (setup time, hold time, clock period) for the asynchronous crossing, the tool can use existing synchronous timing analysis engines without direct modification, thus resolving the contradiction between tool simplicity and analysis accuracy.
2Reliability
If labor-intensive custom assertions and gate-level simulations are used for asynchronous clock domain crossings, then timing analysis accuracy is improved, but verification time increases significantly
Solution Approach 1:
The patent performs preliminary determination of equivalent timing specifications (setup time, hold time, clock period) for asynchronous clock domain crossings before executing the main timing analysis. This preliminary action prepares the data structures and parameters needed for efficient verification, eliminating the need for repeated gate-level simulations and reducing overall verification time while maintaining accuracy.
Solution Approach 2:
The patent creates an equivalent synchronous timing model that copies the essential timing characteristics of the asynchronous crossing into a form that can be analyzed using standard synchronous timing tools. This copying approach avoids the need for complex custom assertions and exhaustive gate-level simulations, significantly reducing verification time while preserving timing analysis accuracy.
3Manufacturing precision
If timing analysis is performed across all signal paths including asynchronous crossings, then timing specification compliance is improved, but analysis complexity increases
Solution Approach 1:
The patent applies local quality by determining equivalent timing specifications specifically for the asynchronous clock domain crossing points, rather than treating the entire design uniformly. The equivalent setup time, hold time, and clock period are calculated locally at the crossing point based on the specific asynchronous path characteristics, allowing precise timing verification without complicating the analysis of other design portions.
Solution Approach 2:
The patent transforms the timing analysis problem by changing parameters at the asynchronous crossing point. It determines equivalent timing parameters (setup time, hold time, clock period) that convert the asynchronous crossing into an equivalent synchronous crossing. This parameter transformation allows standard timing analysis algorithms to be applied, improving specification compliance without substantially increasing overall analysis complexity.
Data Source
AI summary
Various implementations of a method, system, and computer program product for executing timing analysis of an asynchronous clock domain crossing are disclosed. In one embodiment, a signal group and a corresponding timing specification are determined for one or more signals of an electronic design. For each of the signals, a clock associated with the signal is renamed based, at least in part, on the signal group associated with the signal. The asynchronous clock domain between a transmit domain and a receive domain is identified in the electronic design based, at least in part, on identifying a signal path associated with one or more renamed clocks that is asynchronous to a clock associated with the receive domain. For each of the one or more renamed clocks, timing analysis is executed across one or more signals associated with the renamed clock at the asynchronous clock domain crossing.