Multi-Clock Asynchronous Logic Circuit Conversion
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Solution Overview
Problem
Traditional synchronous circuit designs face complexity when dealing with multiple clock domains, especially when clock cycle times are not simple multiples of each other, making it impractical to find a repeating period, which complicates the conversion to asynchronous designs.
Innovation Solution
A method is introduced to associate data tokens with clock domains and determine their durational relationships, allowing for the transformation of synchronous designs with unrelated clock domains into asynchronous designs using up-sampling, down-sampling, or up-down sampling transformation modules, which maintain deterministic behavior without requiring phase lock loops (PLLs).
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If synchronous circuit designs use multiple clock domains with non-simple multiple relationships, then the circuit can handle complex timing requirements, but the design complexity and difficulty of finding repeating periods increases significantly
Solution Approach 1:
The patent introduces an asynchronous interface as an intermediary between clock domains with unrelated frequencies. This interface uses handshaking protocols and buffering mechanisms to translate between different clock domains without requiring a common repeating period, thereby solving the complexity of finding LCM periods while maintaining proper data transfer between domains.
Solution Approach 2:
The patent replaces the traditional synchronous mechanical timing system (which relies on finding common periods and phase relationships) with an asynchronous event-driven system. This substitution eliminates the need to calculate and synchronize to common repeating periods, allowing clock domains with any frequency relationship to coexist without increasing design complexity.
2Adaptability or versatility
If synchronous designs are converted to asynchronous designs, then design flexibility and handling of unrelated clock domains improves, but the conversion process becomes more complex
Solution Approach 1:
The patent segments the conversion process into distinct modules: identification of clock domain boundaries, insertion of asynchronous interfaces at domain boundaries, and transformation of synchronous logic elements into asynchronous equivalents. This segmentation makes the overall conversion process more manageable and systematic.
Solution Approach 2:
The patent performs preliminary analysis to identify all clock domain boundaries and relationships before performing the actual conversion. By pre-processing the design to map out clock domains and their relationships, the subsequent conversion steps become more straightforward and less complex.
3Reliability
If traditional synchronous representations are used, then deterministic behavior and simplified design/testing are achieved, but the ability to handle asynchronous operations is limited
Solution Approach 1:
The patent introduces dynamic handshaking protocols in the asynchronous interfaces that adapt to the timing characteristics of each clock domain. This dynamic approach maintains deterministic behavior within each domain while allowing flexible interaction between domains, bridging the gap between synchronous reliability and asynchronous versatility.
Data Source
AI summary
Methods, systems, and circuits for implementing multi-clock designs in asynchronous logic circuits are described. A method may include associating one or more data tokens with a clock domain of a multi-clock domain netlist. A durational relationship between a clock period associated with the clock domain and one or more other clock domains of the multi-clock domain netlist may be determined. Data tokens used in other clock domains may be transformed based on the determined relationship.