Asynchronous Clock Gating with Glitch-Protected Tristate Buffering
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Tristate buffers in electronic devices often experience glitches when switched into a high impedance state, particularly in asynchronous systems, which can lead to malfunctions due to coincidental switching with clock signal edges.
Innovation Solution
A tristate buffer circuit with a regenerative loop and input delay stage that uses a gating stage to ensure the buffer switches into a high impedance state only when there is no signal transition, preventing glitches by maintaining the output signal level and delaying the switching process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If the tristate buffer is switched asynchronously into a high impedance state, then the switching can occur at any time within a clock period, but this may cause glitches when switching coincides with clock signal edges
Solution Approach 1:
The gating stage checks the input signal and delayed signal before enabling the tristate buffer to switch into high impedance state. This preliminary check ensures that switching only occurs when no signal transition is propagating through the delay stage, preventing glitches while maintaining asynchronous switching capability
Solution Approach 2:
The gating stage acts as an intermediary between the asynchronous tristate signal and the tristate buffer control input. It mediates the switching action by inserting a delay stage and logic gates that monitor signal transitions, allowing asynchronous operation while preventing glitch-causing switchings
2Reliability
If synchronous switching is used, then the clock can only be switched at appropriate moments with a safety margin, but this reduces switching flexibility
Solution Approach 1:
The circuit dynamically adapts the switching behavior based on real-time signal conditions. The gating stage continuously monitors the input signal and delayed signal, enabling the tristate buffer to switch asynchronously when safe, while automatically preventing switching during critical transition periods, thus combining flexibility with reliability
Data Source
Figure 1
Figure 2
Figure 3
AI summary
Atristate buffer circuit includes a tristate buffer switchableinto a high impedance state in response to configuration signal (CS1), a delay stage (DEL) delays the an input signal (BUF-in) to the tristate buffer (TBUF) and a gating stage (GS) having inputs for the input signal (BUF-in), a delayed input signal (BUF-in-DEL) and an asynchronous tristate control signal (3st) and an output supplying the configuration signal (CS1) to the tristate buffer (TBUF). The gating stage (GS) sets the configuration signal (CS1) to the high impedance mode only whenthe tristate control signal (3st) is set and the input signal (BUF-in) and the delayed input signal (BUF-in-DEL) have logic levels indicating that no signal transition of the input signal propagates within the delay stage (DEL). Depending upon signal polarity, the input signal (BUF-in) and the delayed input signal (BUF-in-DEL) are required to have the same digital state or opposite digital states.