Asynchronous Clock Gating Circuit for Early Clock Tree Placement
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Solution Overview
Problem
Conventional clock gating techniques face challenges in reducing power consumption and meeting timing requirements in sequential circuits, particularly due to the construction of clock trees and additional latch-based circuits that increase power dissipation and complicate timing budgets.
Innovation Solution
The design of a multi-utility asynchronous clock gating circuitry that includes a double synchronizer, flip-flops, AND and OR gates, and a multiplexer to synchronize and generate gated clock pulses, allowing for efficient power management and timing compliance by controlling clock signals effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If latch-based clock gating circuit is placed early in the clock tree to save clock tree power, then clock tree power consumption is reduced, but timing budget for setup time requirement is diminished
Solution Approach 1:
The clock gating function is segmented into two independent parts: (1) an asynchronous enable signal processing path that generates gated clock control signals without requiring timing setup, and (2) a synchronous clock distribution path that receives the gated clock signals. This segmentation allows the gating logic to be placed early in the clock tree without compromising timing budgets of the synchronous path.
Solution Approach 2:
An asynchronous enable signal is introduced as an intermediary between the clock source and the clock distribution network. This enable signal passes through synchronization stages (double-flop synchronizer) that convert asynchronous enables into synchronous control signals, mediating between the asynchronous gating requirement and the synchronous clock domain to resolve timing conflicts.
2Loss of time
If plurality of latches are placed later in the clock tree near sequential elements to improve timing budget, then timing requirement is met, but additional power is dissipated by the latches themselves
Solution Approach 1:
The timing-critical latch elements are extracted from the clock gating function and relocated to the data path near sequential elements where they belong. The clock gating function itself is simplified to only generate enable control signals without containing synchronous latches, thereby eliminating the timing budget constraint while minimizing additional power consumption by using only essential gating logic.
3Loss of energy
If conventional clock gating is used to control and optimize power dissipation, then power consumption is reduced, but timing requirements become more complex
Solution Approach 1:
The clock gating mechanism uses periodic clock edges (rising and falling edges) to trigger state changes in the flip-flops that generate gating control signals. By synchronizing the gating control with periodic clock edges rather than requiring continuous timing analysis, the complexity of timing requirements is significantly reduced while maintaining effective power dissipation control.
Data Source
AI summary
The present disclosure envisages an asynchronous clock gating circuitry and a method for designing the asynchronous clock gating circuitry. The asynchronous clock gating circuitry could be placed at the very beginning of the clock network, given its design and implementation logic. The asynchronous clock gating circuitry helps meet the timing requirement on the enable pin thereof. The asynchronous clock gating circuitry avoids cumbersome replication of cluck gating circuitry during physical implementation of the (circuit) design, and further helps reduce the power consumption levels in sequential circuits.