Asynchronous Clock Multiplexing With Flip-Flop Gating to Prevent Glitches
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Solution Overview
Problem
Switching between asynchronous clocks in electronic systems often results in clock glitches, which can cause metastability and system instability due to the potential for runt pulses and frequency mismatches.
Innovation Solution
A glitch reduction circuit utilizing flip-flops and logic gates is introduced to manage the transition between asynchronous clocks, ensuring a glitch-free output by synchronizing the select signal and preventing rapid toggling, even when one clock becomes unreliable or stops functioning.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional clock multiplexing is used to switch between asynchronous clocks, then clock source switching capability is improved, but clock glitches and metastability occur during switchover
Solution Approach 1:
The patent applies preliminary action by generating the inverted select signal before the actual clock switchover occurs. The inverter circuit prepares the complementary signal in advance, ensuring that both clock sources are properly gated before switching, which prevents glitches and metastability during the transition between asynchronous clocks
Solution Approach 2:
The patent uses an inverter circuit as an intermediary element to generate the inverted select signal. This intermediary component ensures that the clock gating logic receives properly synchronized complementary signals, mediating the transition between clock sources and preventing direct conflicts that would cause glitches
2Device complexity
If simple multiplexer control is used for clock switching, then device complexity is reduced, but clock glitches occur during frequency transitions
Solution Approach 1:
The inverter circuit serves as an intermediary that generates the necessary inverted select signal without adding significant complexity to the multiplexer control structure. This intermediary element enables glitch-free switching by ensuring proper synchronization of the clock gating signals
3Speed
If rapid toggling of select signal is allowed, then clock switching responsiveness is improved, but metastability and system instability occur
Solution Approach 1:
The patent applies preliminary anti-action by using the inverter circuit to generate the inverted select signal in advance, which counteracts potential metastability issues before they occur. The pre-generated complementary signal ensures that clock gating transitions are properly synchronized, preventing rapid toggling from causing system instability
Data Source
AI summary
In one embodiment, a method includes receiving an output of a first combinational logic at an enable terminal of a first flip-flop. The first combinational logic inputs include a disable first clock signal from a clock switchover circuit and a disable second clock signal from the clock switchover circuit. A set terminal of the first flip-flop receives an output of a logic gate, and the logic gate receives a select signal and a first clock signal. An input terminal of the first flip-flop receives, an output of a second flip-flop. A reset terminal of the first flip-flop receives an output of a second combinational logic. The second combinational logic inputs include a first clock stopped signal, a power-on-reset signal, and the select signal, the first clock stopped signal indicating a stop in the first clock signal. An output terminal of the first flip-flop outputs a modified select signal.