Asynchronous Clock Interface Circuit for Low-Delay Control Signal Exchange
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Solution Overview
Problem
The exchange of control signals between asynchronous sub-circuits in very large scale integrated circuits is delayed due to the need for separate beating operations in send and receive beat conversion circuits, affecting the performance of asynchronous clock integrated circuits.
Innovation Solution
The implementation of a processing chip with an asynchronous clock interface circuit that includes first and second beat conversion circuits, which simultaneously perform beating operations on control signals entering different clock domains to reduce delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate beating operations are performed in send and receive beat conversion circuits, then control signals can be exchanged between asynchronous sub-circuits, but the delay increases affecting performance
Solution Approach 1:
The patent merges the send beat conversion circuit and receive beat conversion circuit into a single integrated circuit. This integration allows both beating operations to be performed simultaneously on the same hardware platform, eliminating the sequential execution delay that occurred when separate circuits performed operations one after another. The control signal exchange capability is maintained while the time loss is reduced through parallel processing within the unified circuit architecture.
2Adaptability or versatility
If asynchronous clock interface circuit is used between sub-circuits, then control signal exchange is enabled, but the device complexity increases
Solution Approach 1:
The integrated circuit is designed to perform multiple functions: it acts as both a send beat conversion circuit and a receive beat conversion circuit within a single device. This multi-functionality reduces the overall system complexity by eliminating the need for separate dedicated circuits for each function, while still maintaining the full capability for control signal exchange between asynchronous sub-circuits.
Solution Approach 2:
By combining the send and receive beat conversion circuits into one integrated unit, the patent reduces the number of discrete components and interconnections required in the system. This merging simplifies the overall device architecture, reduces routing complexity, and makes the system more manageable while preserving all necessary control signal exchange functions.
Data Source
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AI summary
Embodiments of this application provide a processing chip, a design method, and an electronic device. The processing chip includes a first sub-circuit (10), an asynchronous clock interface circuit (20C), and a second sub-circuit (30). The asynchronous clock interface circuit (20C) includes a first beat conversion circuit (21C), a first trigger circuit (23C), and a second beat conversion circuit (22C). A first signal end (X1) of the first sub-circuit (10) is coupled to a trigger input end (D1) of the first trigger circuit (23C). A trigger output end (Q1) of the first trigger circuit (23C) is separately coupled to an input end of the first beat conversion circuit (21C) and an input end of the second beat conversion circuit (22C). An output end of the first beat conversion circuit (21C) is coupled to a third signal end (X3) of the first sub-circuit (10). An output end of the second beat conversion circuit (22C) is coupled to a second signal end (X2) of the second sub-circuit (30). In embodiments of this application, an exchange delay of an asynchronous clock integrated circuit-based processing chip during asynchronous exchange of a control signal is reduced.