Asynchronous Clock Sampling for Multi-Phase Signal Correction

The patent implements a feedback mechanism where the generated multi-phase signals are fed back to a phase detector that compares their phases. The phase difference information is then used to adjust the delay circuits dynamically, ensuring uniform phase differences despite process variations. This closed-loop feedback system resolves the contradiction by automatically compensating for manufacturing tolerances.

The patent transitions from fixed delay circuits to dynamically adjustable delay circuits controlled by feedback signals. The delay amount is no longer static but is continuously adjusted based on real-time phase difference measurements, enabling the system to adapt to process variations and maintain uniform phase differences across different operating conditions.

The patent changes the sampling strategy by using an asynchronous clock signal with optimized timing parameters. The sampling occurs at specific phases of the asynchronous clock that are strategically chosen to capture accurate phase difference information while minimizing the required sampling frequency. This parameter optimization allows accurate measurement with lower power consumption.

The patent replaces traditional synchronous sampling mechanisms with asynchronous sampling using a digitally controlled oscillator. This substitution eliminates the need for high-frequency synchronous clocks and complex timing synchronization, achieving accurate phase measurement with reduced frequency requirements and lower power consumption.