Asynchronous Clock Interface Circuit for Faster Control Signal Exchange

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Solution Overview

Problem

The exchange of control signals between asynchronous sub-circuits in very large scale integrated circuits is delayed due to the need for separate beating operations in send and receive beat conversion circuits, affecting the performance of asynchronous clock integrated circuits.

Innovation Solution

The implementation of a processing chip with an asynchronous clock interface circuit that includes first and second beat conversion circuits, which simultaneously perform beating operations on control signals entering different clock domains to reduce delay.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If separate beating operations are performed in send and receive beat conversion circuits, then control signals can be converted between different clock domains, but the delay in control signal exchange increases

Engineering Contradiction:

Improvecontrol signal conversion reliabilityVSAvoidcontrol signal exchange delay

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent merges the send beat conversion circuit and receive beat conversion circuit into a single integrated circuit. This integration allows both beating operations to be performed simultaneously rather than sequentially, thereby reducing the total delay in control signal exchange between asynchronous clock domains while maintaining the reliability of signal conversion.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The integrated circuit performs preliminary preparation of both beating operations in advance, allowing the send and receive beat conversion circuits to be ready simultaneously when control signals need to be exchanged. This preliminary action eliminates the sequential waiting time that would otherwise occur between separate beating operations.

Inventive Principle:

Principle #10Preliminary action

2Adaptability or versatility

If an asynchronous clock interface circuit is disposed between asynchronous sub-circuits, then control signal exchange can be achieved, but the circuit complexity increases

Engineering Contradiction:

Improveasynchronous sub-circuit compatibilityVSAvoidinterface circuit complexity

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The integrated circuit is designed with multi-functionality, serving both as a send beat conversion circuit and a receive beat conversion circuit within a single device. This universal design allows the same circuit to handle both directions of control signal conversion between asynchronous sub-circuits, reducing overall system complexity while maintaining full asynchronous compatibility.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS20260081606A1Processing chip, design method, and electronic device

Publication Date: 2026.03.19 HUAWEI TECH CO LTD

AI summary

A processing chip includes a first sub-circuit, an asynchronous clock interface circuit, and a second sub-circuit. The asynchronous clock interface circuit includes a first beat conversion circuit, a first trigger circuit, and a second beat conversion circuit. A first signal end of the first sub-circuit is coupled to a trigger input end of the first trigger circuit. A trigger output end of the first trigger circuit is separately coupled to an input end of the first beat conversion circuit and an input end of the second beat conversion circuit. An output end of the first beat conversion circuit is coupled to a third signal end of the first sub-circuit. An output end of the second beat conversion circuit is coupled to a second signal end of the second sub-circuit.