Asynchronous Clock Domain Simulation Model With Random Delay Selection
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Solution Overview
Problem
Current design simulation methods fail to accurately model the randomness of signal arrival across asynchronous clock domains, potentially masking functional bugs by assuming a fixed delay and neglecting metastability, which can lead to incorrect timing analysis in multi-cycle paths.
Innovation Solution
A simulation model with a three-stage delay network and a selector that randomly chooses between one, two, or three clock cycles delay, driven by a pseudo-random generator, to account for metastability and multi-cycle paths, ensuring accurate modeling of signal arrival and phase alignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a fixed two-clock delay is assumed in simulation, then verification simplicity is improved, but accuracy of timing analysis deteriorates
Solution Approach 1:
The patent applies dynamics by transforming the static fixed delay model into a dynamic variable delay model. The delay is no longer fixed at two clock cycles but varies randomly between 1-3 clock cycles based on metastability events, accurately reflecting real-world behavior while maintaining simulation tractability through controlled randomness.
Solution Approach 2:
The patent changes the delay parameter from a fixed value (2 clocks) to a variable parameter that can take multiple values (1, 2, or 3 clocks) with different probabilities. This parameter transformation allows the simulation to explore multiple timing scenarios without requiring separate fixed-delay simulations for each case.
2Device complexity
If metastability is neglected in simulation, then simulation complexity is reduced, but reliability of verification deteriorates
Solution Approach 1:
The patent introduces an intermediary mechanism (the random delay model) that mediates between the simple fixed-delay assumption and the complex reality of metastability. This intermediary captures the essential effect of metastability (variable delay) without requiring full metastability analysis complexity, thus improving reliability while controlling simulation complexity.
3Stability of the object's composition
If phase alignment between clocks is fixed, then simulation determinism is improved, but accuracy of cross-domain signal modeling deteriorates
Solution Approach 1:
The patent applies preliminary action by pre-determining the possible delay outcomes (1, 2, or 3 clock cycles) and their probabilities before simulation runs. This allows the simulation to incorporate phase alignment variability without requiring dynamic phase tracking during simulation, maintaining determinism while improving accuracy.
Data Source
AI summary
A simulation model for a system wherein data passes from a source domain to a destination domain, such source and destination domains operating with different, asynchronous clocks provided to the source and destination domains. The model includes a three-stage delay network fed by data from the source domain in response to clock provided to operate the source domain. The network operates in response to clocks provided to operate the destination domain. The model includes a selector having inputs fed by outputs of the three delays and an output fed to the destination domain, such selector randomly providing to the output of such selector outputs of the each of the delays from the three stage delay network. The selector output is randomly chosen only when the data in the source domain changes logical state from a logic low to high or from a logic high to low. Otherwise, if this were performed on every clock of the destination domain, the randomness would not be evenly distributed between all three-delay stages.