Asynchronous Clock Sweeping Circuit for SoC Fault Capture
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Solution Overview
Problem
Conventional clock sweeping systems fail to capture faults in data communication associated with clock signals on system-on-chip (SoC) due to same phase relation between clock signals, and are unable to account for on-chip variations, process, voltage, and temperature variations, as well as printed circuit board noises, leading to potential faults being propagated during manufacturing and testing.
Innovation Solution
A clock sweeping system comprising a series of delay elements and a selection circuit that generates asynchronous clock signals by delaying input signals and selecting between them based on control signals, ensuring complete coverage of asynchronous clock signals and capturing faults during silicon validation and testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional clock sweeping system is used to sweep clock signals during RTL simulation and GLS, then clock signals can be swept, but faults in data communication associated with clock signals are not captured due to same phase relation
Solution Approach 1:
The system segments the clock signal processing by introducing multiple delay elements that create different phase versions of clock signals. Each delay element processes the input clock signal independently, generating segmented phase variations that enable comprehensive fault detection across different phase relationships.
Solution Approach 2:
The system dynamically adjusts clock signal phases by varying delay amounts through control signals. The delay elements can be dynamically controlled to produce different phase shifts, enabling the system to adaptively sweep clock signals through various phase relationships to capture faults that occur under different timing conditions.
2Reliability
If conventional clock sweeping system is used, then simulation can proceed, but on-chip variations, PVT variations, and PCB noises lead to unintended phase aligning that prevents fault capture
Solution Approach 1:
The system performs preliminary phase sweeping during simulation to pre-identify potential fault conditions. By proactively generating and testing multiple phase relationships before silicon fabrication, the system prepares comprehensive test vectors that account for anticipated on-chip variations and environmental factors, ensuring faults are captured during silicon validation.
Solution Approach 2:
The system changes the phase parameter of clock signals by adjusting delay amounts in response to simulated on-chip variations, PVT conditions, and noise scenarios. This parameter variation enables the system to test how the design behaves under different timing conditions, ensuring robust fault detection that accounts for real-world variability.
3Productivity
If clock signals maintain same phase relation in conventional system, then simple clock distribution is achieved, but complete coverage of asynchronous clock signals cannot be provided
Solution Approach 1:
The system segments the clock signal path into multiple delay elements, each contributing to the overall phase adjustment. This segmentation allows independent control of phase shifts, enabling comprehensive coverage of asynchronous clock relationships while keeping each individual delay element relatively simple.
Solution Approach 2:
The delay elements and selection circuit serve multiple functions: they generate phase-shifted clock signals, sweep through different phase relationships, and provide controlled asynchronous clock pairs for testing. This multi-functionality achieves complete coverage of asynchronous clock signals without proportionally increasing device complexity.
Data Source
AI summary
A clock sweeping system includes multiple delay elements and a selection circuit. The delay elements are configured to generate multiple delayed clock signals. Each delay element is configured to receive an input signal and delay the input signal to generate a corresponding first delayed clock signal. The input signal is one of a first clock signal, a second clock signal, and a corresponding output signal generated by a previous delay element. The selection circuit is configured to select and output, based on a first select signal for a plurality of times, a corresponding second delayed clock signal as a first output clock signal. The selection circuit is further configured to select and output, based on a second select signal, one of the first and second clock signals as a second output clock signal. The first output clock signal is asynchronous with respect to the second output clock signal.