Asynchronous Clock Switch Without Feedback Loops or Glitches
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional clock switches that multiplex asynchronous clock signals to generate multi-frequency clock signals often suffer from glitches and meta-stable states, which can lead to functional errors, and are not test-friendly due to the use of cross-coupled feedback loops, potentially causing race conditions and requiring reset pins.
Innovation Solution
A clock switch design that avoids cross-coupled feedback loops by using separate clock selection circuits and a multiplexer to switch between two asynchronous clock signals based on feedback signals, ensuring stable transitions and eliminating the need for reset pins, while being compatible with various clock frequencies and phases.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If cross-coupled feedback loops are used to avoid glitches during clock source switching, then clock output stability is improved, but circuit complexity increases and testability deteriorates
Solution Approach 1:
The patent extracts and removes the cross-coupled feedback loop from the clock switching circuit. Instead of using feedback to prevent glitches, the invention uses a straightforward multiplexer-based switching mechanism with separate enable signals for each clock source, eliminating the complex feedback structure while maintaining glitch-free operation through proper signal timing and control.
Solution Approach 2:
The patent segments the clock switching function into independent control paths for each clock source. Each clock source has its own enable signal and control logic, allowing independent management of CLK1 and CLK2 without requiring interdependent feedback loops. This segmentation simplifies the overall circuit structure while maintaining reliable switching behavior.
2Stability of the object's composition
If cross-coupled feedback loops are used to synchronize clock selection, then switching stability is improved, but race conditions may occur and testability deteriorates
Solution Approach 1:
The patent removes the cross-coupled feedback mechanism that causes race conditions and testing difficulties. The invention replaces feedback-based synchronization with independent enable signals controlled by a selection logic unit, eliminating the circular dependency that creates race conditions while maintaining stable switching through proper signal coordination.
3Reliability
If reset pins are required on D flip-flops to establish known states, then circuit reliability is improved, but device complexity and ease of operation worsen
Solution Approach 1:
The patent implements self-service by eliminating the need for external reset pins. The clock switching circuit automatically establishes known states through its inherent control logic and enable signals, which naturally initialize the flip-flops to defined states during normal operation without requiring additional reset control pins or external intervention.
4Adaptability or versatility
If asynchronous clock sources with varying frequencies are supported, then adaptability is improved, but the risk of glitches and meta-stable states increases
Solution Approach 1:
The patent introduces an intermediary selection logic unit that mediates between asynchronous clock sources and the output. This intermediary processes the selection signal and generates coordinated enable signals for each clock source, ensuring that only one asynchronous clock is active at a time and preventing glitches and meta-stable states despite frequency and phase differences between CLK1 and CLK2.
Data Source
AI summary
An improved clock switch in an integrated circuit chip that multiplexes two asynchronous clock signals to generate a multi-frequency clock signal in a manner that avoids glitches on the clock output line and meta-stable states within the switch. The clock switch does not include a cross-coupled feedback loop, thus rendering the clock switch test-friendly and avoiding potential race conditions in the switch. The clock switch is useable with asynchronous clock sources having a variety of different clock frequencies and phases.