Asynchronous Clock-less Logic Path Planning for SWaP Reduction
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Solution Overview
Problem
Current technologies for self-directed vehicles require significant computing power and weight, making it difficult to achieve fast response times and efficient path planning, especially for small and medium-sized drones and robots, due to the need for large power sources and cooling systems, which exceeds the Size, Weight, and Power (SWaP) requirements.
Innovation Solution
A reconfigurable, asynchronous, and clock-less data co-processor with a multidimensional orthogonal array of addressable cells that executes arithmetic operations without a clock, using a Parallelized Asynchronous Digital Logic (ADL) approach, implemented in a small chip size, such as 180 nm process geometries, to achieve low power usage and fast solution times for path planning.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional clock-based digital logic platforms (CPU, GPU, FPGA) are used for path planning, then processing capability is improved, but power consumption and device weight increase significantly
Solution Approach 1:
The system segments the path planning computation into multiple independent processing elements (PEs) organized in a mesh array. Each PE handles a specific portion of the computational domain, allowing parallel processing without requiring a centralized high-power processor. This segmentation enables distributed computation that reduces the power burden on any single component while maintaining overall processing capability.
Solution Approach 2:
The invention replaces traditional clock-based synchronous digital logic with asynchronous event-driven logic. Instead of using a centralized clock signal that requires high-power timing circuits and synchronization logic, the system uses local event-triggered transitions based on data availability. This substitution eliminates the need for high-speed clock distribution networks and reduces dynamic power consumption associated with synchronous operation.
2Measurement precision
If GPU boards with high processing power are implemented, then path planning accuracy is improved, but system size and weight increase due to power sources and cooling systems
Solution Approach 1:
The computational task is divided into multiple independent processing elements arranged in a mesh array, where each PE handles a specific region of the path planning problem. This segmentation allows the system to achieve high computational accuracy through parallel processing of multiple path segments simultaneously, replacing the need for a single high-power GPU while maintaining precision requirements.
Solution Approach 2:
The invention merges computation, storage, and communication functions into integrated processing elements within the mesh array. Each PE contains local memory and processing logic, eliminating the need for separate high-capacity memory modules and high-speed interconnects required by GPU-based systems. This functional integration reduces overall system size and weight while maintaining computational accuracy.
3Loss of time
If high-performance computing systems are used, then response time is reduced, but power consumption increases requiring larger power sources
Solution Approach 1:
The system performs preliminary localization of the computational domain and pre-positions processing elements to handle specific regions of interest. By anticipating which areas require computation and pre-configuring the mesh array accordingly, the system avoids unnecessary processing in low-priority regions, reducing overall computation time and associated power consumption without requiring peak performance from the entire system.
Solution Approach 2:
The asynchronous logic operates in periodic cycles triggered by data availability events rather than a continuous high-speed clock. Processing elements activate only when their input data is ready, creating a periodic rather than continuous operation pattern. This reduces average power consumption while maintaining fast response times for critical path computations by concentrating processing power only when and where needed.
Data Source
AI summary
A hybrid of initial time consuming phase of a Single Directional Dijkstra's Algorithm is embodied on an unclocked CMOS logic chip using a parallelized approach with Asynchronous Digital Logic (ADL). The chip includes a a plurality of addressable configurable cells arranged as a multidimensional orthogonal array. The cell array only executes mathematical operations based on a communication between immediately adjacent cells.