Asynchronous Completion Detector Circuit for Glitch-Free Wide Buses
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Solution Overview
Problem
Existing asynchronous communication systems, particularly in Systems on Chip (SoC) and Networks on Chip (NoC), face performance and productivity limitations due to deep-submicron effects, and conventional completion detection circuits using C-element logic are prone to glitches and are not suited for large-width buses.
Innovation Solution
A completion detector circuit utilizing an asynchronous finite state machine with flip-flops in an inverting loop and logic circuitry to detect stable and de-asserted signal lines, generating signals for completion detection, and employing delay-insensitive coding schemes like dual-rail, m-of-n, and Berger encoding to manage asynchronous data transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If C-element logic is used for completion detection, then the circuit can detect data stability, but it produces glitches and is not suitable for large-width buses
Solution Approach 1:
The completion detection circuit is segmented into multiple independent detection units, each handling a portion of the bus width. Each unit contains its own set of flip-flops and logic gates that independently monitor signal stability on their assigned lines. This segmentation prevents glitches from propagating across the entire bus and allows the system to scale to large widths without degradation.
Solution Approach 2:
Instead of using C-element logic that directly detects completion, the invention inverts the approach by using flip-flops clocked by the data signals themselves to detect when signals become stable. The completion is detected when all flip-flops indicate stability, which is the inverse of the traditional C-element approach and eliminates the glitching behavior inherent in C-elements.
2Reliability
If conventional completion detection circuits are used, then data stability can be detected, but performance and productivity are limited due to deep-submicron effects
Solution Approach 1:
The invention replaces the mechanical C-element logic structure with an asynchronous finite state machine implemented using flip-flops and clocking logic. This substitution eliminates the performance limitations of deep-submicron C-element circuits by using a different detection mechanism that is inherently more suitable for modern fabrication technologies and can operate at higher speeds with better timing characteristics.
3Measurement precision
If the circuit monitors all signal lines for completion, then accurate detection is achieved, but the circuit complexity increases
Solution Approach 1:
The monitoring function is divided into multiple segments, with each detection unit responsible for a specific subset of signal lines. Each unit maintains its own flip-flops and stability detection logic independently. This segmentation reduces the complexity of any single unit while maintaining precise monitoring of all lines through the coordinated operation of multiple simpler units.
Solution Approach 2:
Each detection unit monitors only the portion of the bus assigned to it, performing partial monitoring rather than requiring each unit to monitor all lines. The complete monitoring function is achieved through the aggregation of these partial monitoring results from multiple units, reducing the complexity burden on any single component.
Data Source
AI summary
A completion-detector circuit for detecting completion of the transfer of asynchronous data on a communication channel with signal lines organized according to a delay-insensitive encoding (e.g., dual-rail, m-of-n, Berger encoding) comprises: logic circuitry for detecting the data on the aforesaid signal lines configured for: i) producing a first signal indicating the fact that the asynchronous data on the signal lines are stable; ii) producing a second signal indicating the fact that the signal lines are de-asserted; and an asynchronous finite-state machine supplied with the first signal and the second signal for producing a signal of detection of completion of transfer of the asynchronous data, the detection signal having: a first value, when the first signal is asserted; and a second value, when the second signal is asserted; and being on hold when neither one nor the other of said first signal and said second signal is asserted.