Asynchronous Conversion Circuitry for Synchronous Core Integration

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Solution Overview

Problem

Existing synchronous circuit designs are not easily adaptable for asynchronous application environments, requiring additional time and resources, and existing asynchronous designs lack integration with widely available synchronous core circuitry.

Innovation Solution

Incorporating synchronous circuitry within an asynchronous system, using asynchronous-to-synchronous and synchronous-to-asynchronous conversion circuitry to interface synchronous core circuitry, such as RAM, to operate as an asynchronous block, allowing for the integration of synchronous memory arrays as quasi-delay insensitive black boxes within asynchronous FPGAs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If synchronous circuit designs are used, then ease of manufacture and availability of core circuitry is improved, but adaptability to asynchronous application environments deteriorates

Engineering Contradiction:
Improveease of manufactureVSAvoidadaptability
Core Design Contradiction:
Ease of manufactureVSAdaptability or versatility

Solution Approach 1:

The patent employs conversion circuitry as an intermediary layer between synchronous core circuitry and asynchronous application environments. The asynchronous-to-synchronous conversion circuitry receives asynchronous input signals, converts them to synchronous signals suitable for the core circuitry, and the synchronous-to-asynchronous conversion circuitry converts output signals back to asynchronous format. This mediator approach allows existing synchronous core circuitry to be used in asynchronous applications without direct modification, resolving the contradiction between ease of manufacture and adaptability.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Power

If asynchronous circuit designs are used, then performance and power benefits are improved, but device complexity and design requirements deteriorate

Engineering Contradiction:
Improvepower benefitsVSAvoiddevice complexity
Core Design Contradiction:
PowerVSDevice complexity

Solution Approach 1:

The patent segments the circuit design into distinct functional blocks: asynchronous input interface, asynchronous-to-synchronous conversion circuitry, synchronous core circuitry, synchronous-to-asynchronous conversion circuitry, and asynchronous output interface. This segmentation allows the complex asynchronous handling to be isolated to specific conversion modules while the core circuitry remains simple and well-understood synchronous logic. The modular structure manages device complexity by localizing the complexity burden to dedicated conversion blocks.

Inventive Principle:
Principle #1Segmentation

3Productivity

If synchronous core circuitry is integrated in asynchronous systems, then productivity and design efficiency are improved, but temporal relationship preservation deteriorates

Engineering Contradiction:
Improvedesign efficiencyVSAvoidtemporal relationships
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The conversion circuitry employs feedback mechanisms to preserve temporal relationships between ports. The asynchronous-to-synchronous conversion monitors the asynchronous input signals and uses feedback control to generate appropriate synchronous clock signals that maintain the temporal relationships required by the synchronous core circuitry. Similarly, the synchronous-to-asynchronous conversion uses feedback to ensure output signals maintain proper temporal relationships with the asynchronous interface, thus preserving reliability while enabling productivity gains from using standard synchronous core circuitry.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS8078899B2Asynchronous conversion circuitry apparatus, systems, and methods
Publication Date: 2011.12.13 ACHRONIX SEMICONDUCTOR CORP
  • US8078899B2 patent drawing
  • US8078899B2 patent drawing
  • US8078899B2 patent drawing

AI summary

Apparatus, systems, and methods operate to receive a sufficient number of asynchronous input tokens at the inputs of an asynchronous apparatus to conduct a specified processing operation, some of the tokens decoded to determine an operation type associated with the specified processing operation; to receive an indication that outputs of the asynchronous apparatus are ready to conduct the specified processing operation; to signal a synchronous circuit to process data included in the tokens according to the specified processing operation; and to convert synchronous outputs from the synchronous circuit into asynchronous output tokens to be provided to outputs of the asynchronous apparatus when the synchronous outputs result from the specified processing operation. Additional apparatus, systems, and methods are disclosed.