Asynchronous Processor Core On-Chip Debugging via State Machine
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Solution Overview
Problem
Asynchronous processor cores face challenges in designing interrupt routines due to difficulty in debugging, particularly the lack of on-chip debugging units, which hinders their development and usage in applications like wireless sensor networks and IoT, where on-chip debugging is essential for reading, writing data, and controlling program execution.
Innovation Solution
An asynchronous processor core with a two-state execution control module configured as a automaton, allowing for selective loading and execution of instructions, enabling on-chip debugging by managing a state variable to control the loading of new instruction lines and supporting debugging instructions for suspension and resumption of interrupt routines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If asynchronous processor core is used to reduce energy consumption and improve wake-up time, then energy efficiency and speed are improved, but debugging capability and ease of operation deteriorate due to lack of on-chip debugging unit
Solution Approach 1:
The patent merges the debugging unit with the asynchronous processor core by implementing a state machine that integrates debugging control logic directly into the processor's instruction fetching mechanism. This allows debugging functionality to be embedded within the asynchronous architecture rather than added as a separate synchronous component, maintaining energy efficiency while providing debugging capability.
Solution Approach 2:
The state machine implemented in the patent serves multiple functions: it controls the fetching of instruction lines from memory, manages the execution state of the processor, and provides debugging functionality through pause and resume operations. This multi-functional approach eliminates the need for separate debugging hardware, reducing overall system complexity and energy consumption.
2Speed
If asynchronous logic is implemented to improve execution speed and reduce wake-up time, then performance is improved, but device complexity increases due to difficulty in managing interrupt routines
Solution Approach 1:
The patent segments the processor operation into distinct states (sleep state and execution state) managed by a finite state machine. This segmentation provides clear control over the asynchronous execution flow, making interrupt routine management more predictable and easier to debug while maintaining high execution speed when active.
Solution Approach 2:
The state machine acts as an intermediary between the asynchronous processor core and the external debugging environment. It mediates the fetching of instruction lines and provides a controlled interface for pause and resume operations, simplifying the management of asynchronous interrupt routines while preserving execution performance.
3Ease of operation
If on-chip debugging unit is added to asynchronous processor, then debugging capability is improved, but hardware cost and device complexity increase
Solution Approach 1:
The patent combines debugging functionality with the existing processor state machine by extending its states and transitions to include debugging control. Rather than adding a separate debugging unit, the debugging capabilities are integrated into the instruction fetching and execution control logic, reducing hardware overhead.
Solution Approach 2:
The state machine is designed to perform both normal processor control functions and debugging functions through its state transitions. The same hardware structure that manages instruction fetching also provides pause and resume debugging operations, eliminating the need for dedicated debugging hardware and reducing overall device complexity.
Data Source
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Figure 2
AI summary
This asynchronous processor core (16) includes a sequential instruction line loading unit (56), instruction execution functional units (52, 54, 58, 60, 62), and a decoder (64) for instruction lines loaded by the loading unit (56) into instructions executable by the functional units (52, 54, 58, 60, 62). It includes an execution control module (48) configured as a two-state automaton (74): a sleep state (S1), in which the asynchronous processor core (16) awaits an interrupt command signal to execute an interrupt routine; and an execution state (S2), in which the decoder (64) awaits a new interrupt routine instruction line to decode.The execution control module (48) further manages a status variable of the load unit (56) to selectively allow or prevent, depending at least on the value of this status variable, the loading of a new line of instruction.