Asynchronous Core-Nest Interface for PCI Store Instructions
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Solution Overview
Problem
Existing data processing systems face inefficiencies in handling input/output store instructions, particularly in asynchronous execution and status handling, which can lead to increased cycles per instruction and reduced performance.
Innovation Solution
The proposed data processing system employs an asynchronous core-nest interface and an aggregation buffer to enable asynchronous execution of PCI store instructions, allowing for early completion and efficient data transfer, even when the length of data exceeds eight bytes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If synchronous PCI store instructions are used, then data transfer reliability is ensured, but cycles per instruction increase and system performance decreases
Solution Approach 1:
The patent applies dynamics by transitioning from static synchronous completion to dynamic asynchronous completion. The PCI store instruction no longer blocks the CPU until data transfer completes; instead, the transfer proceeds asynchronously in the background, allowing the system to adapt its execution flow dynamically based on transfer status without waiting for completion.
Solution Approach 2:
The patent implements preliminary action by initiating data transfer before the instruction cycle completes. The PCI store instruction queues the transfer operation and allows the CPU to proceed with subsequent instructions while the data transfer is being executed in the background, effectively performing the transfer action in advance of the traditional completion point.
2Loss of time
If asynchronous execution is implemented, then cycles per instruction are reduced, but status handling complexity increases
Solution Approach 1:
The patent introduces an intermediary mechanism in the form of a status register and completion interrupt system. This intermediary handles the complexity of asynchronous status tracking, allowing the CPU to query transfer status through a dedicated register or receive completion notifications via interrupt, thereby managing asynchronous complexity without burdening the main instruction flow.
3Productivity
If data transfer is performed in background, then CPU throughput is improved, but error detection and notification mechanisms are required
Solution Approach 1:
The patent implements feedback mechanisms through completion interrupts and status registers. The PCI transfer hardware continuously monitors transfer status and provides feedback to the CPU either by updating a status register that the CPU can query or by generating an interrupt signal when transfer completes or encounters an error, enabling the CPU to respond to transfer outcomes without continuous polling.
Data Source
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AI summary
A data processing system (210) and a method for handling an input/output store instruction (30), comprising a system nest (18) communicatively coupled to at least one input/output bus (22) by an input/output bus controller (20). The data processing system (210) further comprises at least a data processing unit (216) comprising a core (12), a system firmware (10) and an asynchronous core-nest interface (14). The data processing unit (216) is communicatively coupled to the system nest (18) via an aggregation buffer (16). The system nest (18) is configured to asynchronously load from and/or store data to an external device (214) which is communicatively coupled to the input/output bus (22). The data processing unit (216) is configured to complete the input/output store instruction (30) before an execution of the input/output store instruction (30) in the system nest (18) is completed.