Asynchronous Counter Timing Error Detection for Digital PLLs
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Solution Overview
Problem
Existing phase-locked loop systems in deep submicron technology rely on analog-intensive phase-frequency detectors and charge pumps, which are inferior and not suitable for digital implementations, necessitating a more effective all-digital timing error detection method.
Innovation Solution
An asynchronous counter-based timing error detector is introduced, comprising an edge detector, time-to-digital converter, and timing error estimator, which processes clocks and dither signals to generate a timing error, utilizing digital outputs to determine both coarse and fine timing errors and reduce reference and fractional spurs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If analog-intensive phase-frequency detector and charge pump are used, then timing error detection can be performed, but the implementation is inferior in deep submicron technology and not suitable for digital implementations
Solution Approach 1:
The patent replaces the analog-intensive phase-frequency detector and charge pump with an all-digital implementation using asynchronous counters and digital logic circuits. This substitution transitions the system from analog to digital domain, making it suitable for deep submicron technology where digital circuits offer better reliability and scalability.
Solution Approach 2:
The invention changes the fundamental operating parameters by using digital signals and counting mechanisms instead of analog voltage and current relationships. The timing error detection is achieved through digital counter values and logical comparisons rather than analog charge pumping, fundamentally altering the detection mechanism to be digital-native.
2Measurement precision
If conventional phase-frequency detector is used, then timing relationship can be detected, but measurement precision is insufficient for high-accuracy applications
Solution Approach 1:
The timing error detection is segmented into multiple independent counter operations. The first counter detects rising edges of the first clock, the second counter detects rising edges of the second clock, and a third counter detects transitions of the dither signal. This segmentation allows each counter to specialize in specific timing measurements, improving overall precision.
Solution Approach 2:
The patent introduces a dither signal as an intermediary element to enhance timing measurement precision. The dither signal modulates the sampling process, allowing the system to resolve timing differences that would be indistinguishable in a direct comparison, effectively acting as a precision-enhancing mediator.
3Ease of manufacture
If all-digital implementation is used, then suitability for deep submicron technology improves, but device complexity increases
Solution Approach 1:
The asynchronous counter structure is designed to be multi-functional, serving both as a frequency divider and a timing error detector. The same counter circuitry that counts clock cycles also provides the timing difference information when compared between different clock domains, reducing the need for separate dedicated circuits.
Solution Approach 2:
The digital counters automatically perform their counting and comparison functions without requiring external analog control circuits. The system uses its own digital outputs and logical operations to generate timing error signals, making the digital implementation self-sufficient and eliminating the need for hybrid analog-digital interfaces.
Data Source
AI summary
A method for estimating a timing difference between a first clock signal and a second clock signal is disclosed. The estimating method comprising: generating an edge signal by detecting an edge of the second clock signal by sampling the second clock signal using the first clock signal; generating a delayed edge signal by a further sampling of the second clock signal using the first clock signal; generating a first intermediate code by counting a number of clock edges of the first clock signal within a duration defined by the edge signal using an asynchronous counter; generating a second intermediate code to represent a timing difference between the second clock signal and the delayed edge signal using a time-to-digital converter; and generating an output code using a weighted sum of the first intermediate code and the second intermediate code.