Asynchronous Current-Mode ADCs for Low-Power AI Signal Conversion
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Solution Overview
Problem
Conventional analog-to-digital converters (ADCs), particularly current-mode ADCs, face challenges in operating with low voltage power supplies, experiencing glitches, and requiring high power consumption, large die size, and complex circuitry, which limits their performance and accuracy in low-power applications.
Innovation Solution
The development of a current-mode signal conditioning system with multi-staged current-mode analog-to-digital converters (iADCs) that operate asynchronously, decouple analog and digital computations, and use scaled reference current sources to condition current signals, allowing for zero-to-full scale input signals with low voltage power supplies, reducing power consumption, and eliminating the need for passive components like resistors and capacitors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If voltage-mode ADCs with switch-capacitor techniques are used, then low offset and low noise performance is achieved, but the range of input voltage signals is limited to the maximum available power supply voltage
Solution Approach 1:
The patent replaces voltage-mode operation with current-mode operation. Current-mode ADCs process signals using current instead of voltage, allowing the input signal range to extend beyond the power supply voltage range while maintaining good offset and noise characteristics through current-based signal processing.
Solution Approach 2:
The patent changes the fundamental operating parameter from voltage to current. By operating ADCs in current-mode with FETs in the subthreshold region, the system achieves ultra-low power consumption while expanding the input signal range to span zero to full scale independently of the low voltage supply amplitude.
2Temperature
If switch-capacitor techniques are used to pump-up internal power supply voltage, then low power supply voltage operation is enabled, but circuit complexity and cost increase
Solution Approach 1:
The patent eliminates switch-capacitor voltage pumping by directly designing current-mode ADCs that operate natively from low voltage power supplies. This substitution removes the need for complex voltage multiplication circuitry while maintaining compatibility with low voltage operation.
Solution Approach 2:
The patent extracts and removes the switch-capacitor voltage pumping stage from the system. By using current-mode operation, the ADC can directly interface with low voltage supplies without requiring the intermediate voltage boosting mechanism, thereby simplifying the overall circuit architecture.
3Duration of action of moving object
If voltage-mode ADCs are used, then sample and hold capability is provided, but transient response is impeded and input-to-output glitch rejection is degraded
Solution Approach 1:
The patent replaces voltage-mode sample and hold circuits with current-mode equivalents. Current-mode operation provides inherently faster transient response because current changes can occur more rapidly than voltage changes, while still maintaining the ability to perform sampling and holding functions through current storage elements.
4Extent of automation
If free running clocks are used in voltage-mode ADCs, then clocked operation is achieved, but dynamic power consumption increases and digital system noise is raised
Solution Approach 1:
The patent transitions from continuous free-running clock operation to periodic or event-driven operation. Current-mode ADCs can be triggered by external events or use asynchronous operation, eliminating the need for continuous clocking and thereby reducing dynamic power consumption and associated digital noise.
Solution Approach 2:
The patent extracts and removes the free-running clock generator from the system. By using event-triggered or asynchronous current-mode operation, the continuous clock signal is eliminated, removing its associated dynamic power consumption and digital noise from the system.
5Speed
If conventional flash based iADCs are used, then high speed conversion is achieved, but power consumption increases and accuracy is degraded due to signal copying
Solution Approach 1:
The patent segments the ADC into multiple current-mode stages operating in sequence rather than using a single large flash converter. This segmentation allows each stage to process current signals directly without copying, maintaining accuracy while achieving high speed through the inherent speed of current-mode operation and parallel processing across stages.
6Measurement precision
If increasing resolution of flash iADC is implemented, then measurement precision is improved, but die area and power consumption increase exponentially
Solution Approach 1:
The patent divides a high-resolution ADC into multiple lower-resolution current-mode stages that process signals sequentially. Each stage handles a portion of the total resolution requirement, allowing the system to achieve high overall resolution without requiring an exponentially large single-stage flash converter, thereby controlling die area and power consumption.
Solution Approach 2:
The patent transitions from a single-dimensional flash converter architecture to a multi-dimensional cascaded current-mode architecture. By distributing the conversion function across multiple stages operating in sequence, the system achieves high resolution without the exponential area and power penalty of a single-stage approach.
Data Source
AI summary
Single-stage and multiple-stage current-mode Analog-to-Digital converters (iADC)s utilizing apparatuses, circuits, and methods are described in this disclosure. The disclosed iADCs can operate asynchronously and be free from the digital clock noise, which also lowers dynamic power consumption, and reduces circuitry overhead associated with free running clocks. For their pseudo-flash operations, the disclosed iADCs do not require their input current signals to be replicated which saves area, lowers power consumption, and improves accuracy. Moreover, the disclosed methods of multi-staging of iADCs increase their resolutions while keeping current consumption and die size (cost) low. The iADC's asynchronous topology facilitates decoupling analog-computations from digital-computations, which helps reduce glitch, and facilitates gradual degradation (instead of an abrupt drop) of iADC's accuracy with increased input current signal frequency. The iADCs can be arranged with minimal digital circuitry (i.e., be digital-light), thereby saving on die size and dynamic power consumption.