Asynchronous Data Acquisition With Anti-Jitter Storage Flags
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Solution Overview
Problem
Digital pre-distortion technologies for power amplifiers in wireless communication systems are limited to cases where the clock domains of downlink and feedback data are the same, restricting their application range due to asynchronous clock issues, which cause phase jitter and affect the delay consistency between acquired data.
Innovation Solution
A data acquisition method and apparatus that perform anti-jitter processing on storage flags to synchronize data acquisition across asynchronous clock domains, ensuring a consistent delay between downlink and feedback data, thereby expanding the application range to include scenarios with different clock domains.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If digital pre-distortion technology is used to cancel nonlinear distortion caused by power amplifier, then distortion characteristics are improved, but application range is limited to synchronous clock domains only
Solution Approach 1:
The patent changes the clock domain parameter from synchronous to asynchronous operation. By implementing anti-jitter processing mechanisms that can handle variable clock frequencies and phases, the system expands its operational parameters to include asynchronous clock domains while maintaining distortion cancellation performance.
Solution Approach 2:
The patent introduces an intermediary anti-jitter processing module between the data acquisition stages. This intermediary component synchronizes asynchronous clocks by performing jitter correction and phase alignment, enabling the system to bridge different clock domains while maintaining data integrity for pre-distortion processing.
2Adaptability or versatility
If data acquisition is performed across asynchronous clock domains, then application range is expanded, but phase jitter occurs affecting delay consistency
Solution Approach 1:
The patent introduces an intermediary anti-jitter processing module between the data acquisition stages. This intermediary component synchronizes asynchronous clocks by performing jitter correction and phase alignment, enabling the system to bridge different clock domains while maintaining data integrity for pre-distortion processing.
Solution Approach 2:
The patent performs preliminary anti-jitter processing on the feedback data before it enters the pre-distortion calculation stage. By pre-synchronizing the asynchronous clocks and correcting phase jitter in advance, the system ensures that delay consistency is maintained throughout subsequent processing stages.
3Manufacturing precision
If anti-jitter processing is performed on storage flag to synchronize data acquisition, then delay consistency is improved, but processing complexity increases
Solution Approach 1:
The patent extracts the jitter correction functionality into a dedicated anti-jitter processing module that operates specifically on the storage flag. By isolating this complex processing task into a separate component, the main pre-distortion processing logic remains simple while the specialized module handles the complexity of asynchronous clock synchronization.
Solution Approach 2:
The anti-jitter processing module performs self-service by automatically detecting and correcting phase jitter without requiring external intervention. The module monitors the storage flag transitions and autonomously adjusts timing to maintain delay consistency, reducing the need for complex external control mechanisms.
Data Source
AI summary
The present application provides a data acquisition method, a data acquisition apparatus, a data acquisition device and a storage medium. The data acquisition method includes: obtaining a first storage flag for indicating a flag bit at which first data starts to be acquired and stored; when a first data acquisition clock is asynchronous with a second data acquisition clock, obtaining a second storage flag being a storage flag bit corresponding to the first storage flag after the first storage flag crosses from the first data acquisition cock to the second data acquisition clock, according to the first data acquisition clock and the second data acquisition clock; and performing anti-jitter processing on the second storage flag to obtain a third storage flag, and acquiring second data according to the third storage flag, a delay between the first data and the second data acquired each time is kept unchanged.