Asynchronous Data Transmission Buffers for IC Critical Paths
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Solution Overview
Problem
Conventional integrated circuit devices face inefficiencies in data transfer due to high area overhead for synchronous communication, requiring complex timing control circuits and additional circuits for multiple voltage and frequency domains, which leads to increased complexity and potential errors.
Innovation Solution
The implementation of a circuit for asynchronous data transmission using a transmitter circuit, asynchronous buffers, and receiver circuits, which allows for data to be generated and stored in response to a clock signal, enabling asynchronous pipelining and reducing the need for registers along critical paths, thereby increasing throughput and flexibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If synchronous communication is used with clock signals, then data transfer reliability is improved, but area overhead and device complexity increase
Solution Approach 1:
The patent extracts the clock signal dependency from the data transfer path by introducing asynchronous buffers that operate independently of global clock signals. The buffers use local timing information and handshaking protocols to transfer data without requiring synchronous clock distribution, thereby eliminating complex timing control circuits while maintaining reliable data transfer.
Solution Approach 2:
The patent introduces asynchronous buffers as intermediary elements between transmitter and receiver circuits. These buffers act as mediators that decouple the timing domains of different parts of the circuit, allowing data to be transferred reliably without requiring synchronized clock signals across the entire system.
2Adaptability or versatility
If multiple voltage and frequency domains are implemented, then adaptability is improved, but additional circuits and complexity increase
Solution Approach 1:
The patent segments the circuit into independent transmitter, buffer, and receiver modules that can operate in different voltage and frequency domains. Each segment is self-contained with its own timing control, allowing them to be configured for different operational domains without requiring complex inter-domain timing synchronization circuits.
Solution Approach 2:
The patent implements dynamic configuration capabilities where the asynchronous buffers can adapt their operating parameters (voltage, frequency) based on the specific requirements of the connected transmitter and receiver circuits. This dynamic adaptability allows the system to accommodate multiple voltage and frequency domains without requiring dedicated circuits for each domain combination.
3Manufacturing precision
If registers are placed along critical paths for timing control, then data transfer accuracy is improved, but area overhead increases
Solution Approach 1:
The patent replaces traditional register-based timing control with asynchronous buffers that act as intermediaries. These buffers provide the necessary timing control and data latching functionality without requiring the same amount of area as conventional registers, thereby reducing area overhead while maintaining data transfer accuracy through their asynchronous handshaking mechanism.
4Area of stationary object
If asynchronous buffers are used instead of registers, then area overhead is reduced, but timing control complexity increases
Solution Approach 1:
The asynchronous buffers are designed to be self-sufficient in their timing control, using local feedback signals and handshaking protocols to automatically manage data transfer timing. This self-service capability eliminates the need for external timing control circuits, thereby reducing both area overhead and timing control complexity compared to traditional register-based approaches.
Data Source
AI summary
A circuit for asynchronously transmitting data in an integrated circuit is described. The circuit comprises a transmitter circuit generating data to be transmitted at an output; a first register having an input, an output and a clock input, wherein the input of the first register is coupled to the output of the transmitter and the clock input of the first register is coupled to receive a clock signal; at least one asynchronous buffer having an input and an output, wherein the input is coupled to the output of the first register; a receiver circuit coupled to the output of the at least one buffer; and a second register having an input, and output and a clock input, wherein the input of the at least one asynchronous buffer is coupled to the output of the transmitter and the clock input of the second register is coupled to receive the clock signal. A method of implementing of asynchronously transmitting data in an integrated circuit device is also disclosed.