Asynchronous Data Interface Buffer with Dual Clock Domain Pointers
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Solution Overview
Problem
Existing asynchronous data interfaces face challenges in synchronizing data between clock domains with different frequencies, requiring additional time and resources for frequency calculation and limiting data transmission until metastability is resolved, which restricts writing subsequent data until current data is read.
Innovation Solution
A data interface system utilizing a buffer and pointers that function across both clock domains, allowing continuous data transmission by using write and read pointers to determine buffer fullness or emptiness, enabling asynchronous data transfer without relying on fixed frequency or phase relationships.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If frequency calculation is used to synchronize data between clock domains, then data transmission can be achieved, but additional system time and resources are required
Solution Approach 1:
The patent extracts the frequency calculation requirement from the data transmission process by using a buffer that operates independently of clock frequency relationships. The buffer decouples the source and destination clock domains, allowing data to be transferred without calculating or knowing the frequency relationship between them.
Solution Approach 2:
The buffer serves as an intermediary between the source and destination clock domains. It mediates the data transfer by accepting data from the source clock domain and making it available to the destination clock domain without requiring direct frequency coordination between the two domains.
2Reliability
If single bit acknowledgment is used to resolve metastability, then data can be safely transferred between clock domains, but subsequent data writing is limited until current data is read
Solution Approach 1:
The patent segments the data transfer process into independent write and read operations using separate pointers. The write pointer tracks data written by the source while the read pointer tracks data read by the destination, allowing multiple data items to be in various stages of transfer simultaneously rather than requiring sequential acknowledgment.
Solution Approach 2:
The buffer enables continuous data transfer by maintaining a pool of data that can be read from while more data is being written. The write and read pointers allow the system to continuously operate with multiple data items in flight, eliminating the idle waiting periods inherent in single-bit acknowledgment protocols.
3Reliability
If fixed frequency difference is used for data transfer, then data can be transmitted between clock domains, but the frequencies need to be known and calculated
Solution Approach 1:
The patent removes the frequency calculation requirement from the system by using a buffer that operates independently of clock frequency relationships. The buffer absorbs the frequency differences between source and destination domains, eliminating the need for frequency measurement, calculation, or coordination hardware.
4Adaptability or versatility
If single bit acknowledgment protocol is used, then data can be safely transferred independent of clock ratios, but the source side must wait for acknowledgment before writing new data
Solution Approach 1:
The patent segments the data transfer into independent write and read operations tracked by separate pointers. This allows the source to continue writing data with multiple write pointers indicating different data items at different stages of transfer, while the destination reads at its own pace, maintaining clock ratio independence without stalling the source.
Solution Approach 2:
The buffer enables continuous writing by the source and reading by the destination simultaneously. Multiple data items can be in various stages of transfer at the same time, with write and read pointers tracking their respective positions, eliminating the stop-and-wait behavior of single-bit acknowledgment protocols.
Data Source
AI summary
A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design, the design structure comprising for an interface system is disclosed. The system includes a buffer that receives data from a source in a first clock domain and stores the data to be read by a destination in a second clock domain, wherein the buffer functions in both the first clock domain and the second clock domain; a write pointer that points to data written by the source; and a read pointer that points to data read by the destination. According to the design structure, the write pointer and the read pointer are utilized to enable the data to be transmitted from the first clock domain to the second clock domain asynchronously.