Asynchronous Data Port Clock-Domain Conversion for Noise Isolation
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Solution Overview
Problem
State-of-the-art audio and video systems face challenges in managing noise within multiple-format integrated circuits, particularly when operating in asynchronous modes, as noise coupling occurs between on-chip circuits due to unsynchronized clock signals in multiple data paths.
Innovation Solution
A data processing system with an input data port for asynchronous data reception, sample rate converters to synchronize data with a native clock signal, and converters to ensure all data streams operate within a unified clock domain, minimizing noise coupling by spacing switching events appropriately.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple-format integrated circuits include ADCs, DACs, and PWM controllers on a single chip, then functionality and integration are improved, but on-chip noise coupling increases
Solution Approach 1:
The patent segments the clock domains by introducing a separate asynchronous clock signal path for the serial data port, distinct from the native clocks driving ADCs, DACs, and PWM controllers. This segmentation isolates noise sources in different functional blocks, preventing noise coupling between them while maintaining multiple-format integration on a single chip.
Solution Approach 2:
The patent introduces an intermediary asynchronous serial data port interface that mediates between externally synchronized data streams and the internal multiple-format converter circuitry. This intermediary port operates with its own clock domain, acting as a buffer that prevents direct noise coupling between external data sources and internal converters while preserving functionality.
2Adaptability or versatility
If asynchronous serial data port is used for data exchange, then operational flexibility is improved, but noise management complexity increases
Solution Approach 1:
The patent merges the asynchronous serial data port functionality with the multiple-format converter circuitry into a unified integrated circuit design. By combining these functions on a single chip with a shared physical platform but separate clock domains, the patent reduces overall system complexity compared to using multiple separate components, while maintaining asynchronous operation capability for flexible data exchange.
3Object-affected harmful factors
If all data streams are synchronized to a single clock domain, then noise coupling is reduced, but operational flexibility for asynchronous data ports is limited
Solution Approach 1:
The patent implements dynamic clock domain management where the serial data port operates in an asynchronous clock domain when receiving external data streams, and can be dynamically synchronized to the native clock domain when interfacing with internal converters. This dynamic switching between operational modes allows the system to reduce noise coupling through synchronization when needed while maintaining asynchronous operation flexibility when required.
Data Source
AI summary
A data processing system including an input data port for receiving input data samples asynchronous to a native clock signal and having an input sample rate, a first sample rate converter for converting the data samples from the input sample rate to a sample rate synchronous with a rate of the native clock signal, and a data converter for converting data samples output from the first sample rate converter to another format. An analog to digital converter converts an analog signal into output data samples with a sample rate synchronous with the rate of the native clock signal, and a second sample rate converter converts the sample rate of the output data samples from the sample rate synchronous with the rate of the native clock signal to an output sample rate such that output data samples are asynchronous to the native clock signal.