Asynchronous Delay Comparator Stages for Low-Metastability ADCs
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Solution Overview
Problem
Analog-to-digital converters face challenges in operating at high speed with low power consumption and minimal meta-stability while occupying a small area, as existing solutions often require large areas and are prone to meta-stability issues.
Innovation Solution
The proposed analog-to-digital converter system employs a delay comparator with a comparator circuit and sign-out/delay-out circuits, operating asynchronously without a clock, and uses multiple stages with AND gates and delay comparators to generate digital signals representing the order and delay of input signals, allowing for efficient processing and reduced meta-stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional analog-to-digital converter architectures are used, then conversion functionality is achieved, but the converter requires large area and is prone to meta-stability issues
Solution Approach 1:
The converter is divided into multiple independent delay stages, each processing a portion of the conversion task. This segmentation eliminates meta-stability by ensuring each stage completes its operation before passing control to the next stage, while the modular structure reduces overall area requirements compared to a single large converter block.
Solution Approach 2:
The patent replaces traditional clocked synchronous logic with an asynchronous delay-based mechanism. Instead of using clock signals and flip-flops that require large decision blocks, the system uses variable delay elements and timing relationships to achieve conversion, eliminating meta-stability and reducing area.
2Speed
If high-speed operation is implemented, then conversion speed increases, but power consumption increases and meta-stability occurs
Solution Approach 1:
The converter uses dynamic delay adjustment where each stage's delay is adaptively controlled based on the input signal characteristics. This allows the system to operate at high speed when needed while consuming less power during lower-speed operations, avoiding the meta-stability associated with fixed high-speed clocked architectures.
Solution Approach 2:
The conversion process is broken into periodic delay stages that operate sequentially rather than simultaneously. Each stage processes the signal for a predetermined delay period, then passes control to the next stage. This periodic operation achieves high effective conversion speed while keeping instantaneous power consumption low.
3Ease of operation
If clocked operation is used, then timing control is achieved, but the converter requires large area for decision blocks and clock distribution
Solution Approach 1:
The patent substitutes clocked synchronous control with an asynchronous delay-based control mechanism. Timing is achieved through predetermined delay elements and signal propagation timing rather than clock signals. This eliminates the need for large decision blocks and clock distribution networks, significantly reducing converter area while maintaining precise timing control.
Data Source
AI summary
A clock-less delay comparator coupled to a first input signal and a second input signal, the clock-less delay comparator comprising: a first transistor having a control terminal coupled to the second input signal, a first current terminal coupled to a first voltage supply, and a second current terminal; a second transistor having a control terminal, a first current terminal coupled to the first voltage supply, and a second current terminal; a third transistor having a control terminal, a first current terminal coupled to the first voltage supply, and a second current terminal; a fourth transistor having a control terminal coupled to the first input signal, a first current terminal coupled to the first voltage supply, and a second current terminal; a fifth transistor having a control terminal coupled to the second input signal, a first current terminal, and a second current terminal coupled to the control terminal of the third transistor; a sixth transistor having a control terminal coupled to the first input signal, a first current terminal, and a second current terminal coupled to the control terminal of the second transistor and the second current terminal of the third transistor; a seventh transistor having a control terminal coupled to the control terminal of the second transistor, a first current terminal coupled to a second voltage supply, and a second current terminal coupled to the first current terminal of the fifth transistor; an eighth transistor having a control terminal coupled to the control terminal of the third transistor, a first current terminal coupled to the second voltage supply, and a second current terminal coupled to the first current terminal of the sixth transistor; a ninth transistor having a control terminal coupled to the first input signal, a first current terminal coupled to the second current terminal of the first transistor, and a second current terminal coupled to the second current terminal of the second transistor and the second current terminal of the fifth transistor; and a tenth transistor having a control terminal coupled to the second input signal, a first current terminal coupled to the second terminal of the fourth transistor, and a second current terminal coupled to the second current terminal of the third transistor.