Asynchronous Digital Communication Module Clock Synchronization
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Solution Overview
Problem
Asynchronous serial communication methods face challenges in maintaining clock synchronization between transmitting and receiving ends without a separate synchronization signal, leading to errors due to clock jitter and increased system costs, with existing encoding methods like Manchester code and bipolar code suffering from bandwidth loss and error issues.
Innovation Solution
A digital communication system that encodes digital bits into voltage pulses using a clock generator and voltage encoder, where the voltage pulse maintains a first voltage level during certain periods and transitions to a second level in an impulse form, allowing the client device to decode and synchronize the clock signal without a separate synchronization line.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If synchronous communication is used with a separate synchronization signal, then clock synchronization is improved, but device complexity and cost increase
Solution Approach 1:
The patent combines the data signal and clock signal into a single transmitted signal. The transmitted signal modulates the clock signal with data information, allowing the receiver to extract both data and clock synchronization information from one channel, thereby eliminating the need for separate synchronization lines while maintaining reliable clock synchronization.
Solution Approach 2:
The transmitted signal serves multiple functions simultaneously: it carries data information and provides clock synchronization reference. The receiver can decode both the data bits and regenerate the clock signal from the same received signal, making the communication system more efficient and less complex.
2Device complexity
If asynchronous serial communication is used with a single power line, then device complexity is reduced, but clock error increases due to jitter
Solution Approach 1:
The patent implements a feedback mechanism where the receiver extracts clock synchronization information from the received signal and regenerates the clock signal. This regenerated clock is then used to sample and decode the data, creating a closed-loop system that compensates for jitter and clock errors without requiring separate synchronization lines.
Solution Approach 2:
The transmitted signal is pre-modulated to contain clock synchronization information that the receiver can extract in advance before data decoding. This preliminary extraction of clock information allows the receiver to prepare the correct sampling timing before actual data reception, reducing the impact of jitter.
3Reliability
If Manchester code or bipolar code is used for encoding, then clock synchronization is improved, but bandwidth is lost or error rates increase
Solution Approach 1:
The patent changes the encoding parameters by modulating the clock signal directly with data information rather than using traditional line encoding schemes like Manchester or bipolar codes. This approach maintains the clock synchronization benefits while avoiding the bandwidth overhead associated with these traditional encoding methods, as the data is embedded in the clock signal transitions rather than requiring separate encoding.
Data Source
AI summary
Provided is a digital transmitting module included in a host device connectable to a client device. The digital transmitting module may include: a clock generator which provides the host device with a clock whose one cycle is composed of T1, T2, T3 and T4 connected sequentially; and a voltage encoder which receives the clock from the clock generator, receives a digital bit from the host device, generates a voltage pulse by encoding the digital bit based on the clock, and then transmits the voltage pulse to the client device. Provided is a digital receiving module included in a client device connectable to a host device. The digital receiving module may include: an inpulse extractor which receives a voltage pulse from the host device and generates an inpulse signal by referring to an inpulse component of the voltage pulse; a voltage decoder which decodes a digital bit by referring to the inpulse signal; and a clock synchronizer which generates a clock synchronized with a clock signal of the host device by referring to the inpulse component existing in each cycle of the inpulse signal.