Asynchronous Error Correction Circuit Reducing Die Area and Power
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Solution Overview
Problem
Error correction circuits in electronics are susceptible to PVT variations and require significant circuitry, power, and complexity, often necessitating external controls and clocks, which increases costs and die area.
Innovation Solution
An asynchronous error correction circuit that processes digit streams with Hamming codes, implemented using asynchronous logic and antifuse technology, allowing operation without external clocks or controls, and consuming less power and die area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional error correction circuits are used, then error correction capability is provided, but circuit complexity and die area increase
Solution Approach 1:
The patent extracts and eliminates external control and clock circuits from the error correction system, making the ECC circuit self-contained and autonomous. This removal of external dependencies directly reduces device complexity while preserving error correction functionality through internal state machine design.
Solution Approach 2:
The error correction circuit is designed to handle multiple error correction codes (Hamming, BCH, Reed-Solomon) and various memory types through a unified architecture. This multi-functionality reduces overall system complexity by replacing multiple specialized circuits with a single versatile error correction engine.
2Reliability
If traditional error correction circuits are used, then error correction capability is provided, but die area increases
Solution Approach 1:
The patent merges the control logic, state machines, and error correction algorithms into a single integrated circuit block. By combining multiple functional elements that were previously separate (control circuits, clock generators, and ECC logic) into one unified structure, the die area is significantly reduced while maintaining full error correction capability.
3Reliability
If external controls and clocks are used, then error correction operation is enabled, but power consumption increases
Solution Approach 1:
The error correction circuit is designed to be self-starting and self-regulating, with internal state machines that automatically manage the correction process without external control signals. This self-service capability eliminates the power consumption associated with external control logic and clock distribution, while ensuring reliable error correction operation through autonomous internal control.
Data Source
AI summary
This disclosure relates to error correction circuitry. In one aspect, an error correction circuit can serially receive a digit stream and parse the digit stream into substrings of a predetermined length of digits. Each of the substrings can include data digits and parity digits in certain embodiments. As the substring is received, parity can be tracked in defined regions of the substring. When the entire substring has been received, an error in one of the data digits of the substring can be corrected based on an indication of parity in at least one defined region in some embodiments. Then corrected data, which can include the corrected data digit and the other data digits of the substring, can be stored. According to certain embodiments, the error correction circuit can be implemented by asynchronous circuitry.