Asynchronous FIFO Clock Synchronization Without Full-Empty Logic
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Solution Overview
Problem
Existing asynchronous FIFO circuits face complications in control due to the need for full/empty determination circuits, especially when data width is wide, leading to increased latency and complexity in transfer timing.
Innovation Solution
An asynchronous FIFO circuit with separate write and read clock domains using phase locked loops (PLLs) to generate synchronized write and read clocks, along with control signal generation units, simplifying data transfer by eliminating the need for full/empty determination and reducing latency through synchronized write and read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a full/empty determination circuit is provided, then data transfer control is achieved, but control complexity increases and buffer requirements increase
Solution Approach 1:
The patent extracts and eliminates the full/empty determination circuit from the asynchronous FIFO system. Instead of using pointer comparison to determine full/empty status, the invention uses separate write and read clock domains with independent control, removing the need for complex control logic while maintaining reliable data transfer control.
Solution Approach 2:
The patent segments the FIFO control into separate write and read clock domains, each with independent control logic. This segmentation allows write and read operations to be controlled independently without needing to determine full/empty status through pointer comparison, thereby reducing control complexity.
2Productivity
If data width is increased, then data transfer capacity is improved, but transfer timing discrepancies increase and control becomes more complicated
Solution Approach 1:
The patent segments the data transfer control into separate write and read clock domains with independent control logic. This segmentation allows each domain to control its own timing independently, eliminating transfer timing discrepancies that occur with wide data widths in conventional shared-clock systems.
Solution Approach 2:
The patent introduces dynamic clock domain separation where write and read operations occur in different clock domains with independent timing control. This dynamic approach allows the system to handle wide data widths without timing discrepancies, as each domain can synchronize its own operations independently.
3Reliability
If pointer comparison is used to check data delivery, then data transfer monitoring is achieved, but latency from writing to reading increases
Solution Approach 1:
The patent extracts and eliminates the pointer comparison mechanism from the system. Instead of monitoring data delivery through write-to-read pointer comparison, the invention uses separate clock domains with independent control signals, removing the source of latency while maintaining reliable data transfer monitoring through dedicated control logic.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides a simplified control mechanism and reduces latency in data transfer by ensuring write and read operations are synchronized, allowing for efficient handling of wide data widths without the need for complex full/empty determination circuits.
Implementation Method 1
a write clock generation unit that generates, from an input clock, a write clock to be used in write processing; a read clock generation unit that generates, from the input clock, a read clock to be used in read processing
Data Source
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AI summary
An asynchronous FIFO circuit of the present invention generates a write clock and a read clock from the same input clock, and generates a write control signal in synchronization with the write clock and a read control signal in synchronization with the read clock. The asynchronous FIFO circuit includes a data read-write unit having a plurality of data holding units. The data read-write unit writes data into one of the data holding units for each write clock on the basis of the write control signal, and reads data from one of the data holding units for each read clock on the basis of the read control signal.