Asynchronous FIFO Buffer Using Event Transfer Blocks
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Solution Overview
Problem
Asynchronous first-in-first-out (FIFO) buffers used for high-bandwidth data transfer between memory and compute logic domains in machine learning accelerators are expensive in terms of area consumption and power consumption, and have a predetermined number of entries that limit efficiency.
Innovation Solution
The implementation of an area efficient asynchronous FIFO buffer using an event transfer block with a credit/debit mechanism, which decouples pointers and counters to support non-power of two, including odd, number of entries, reducing area and power consumption while simplifying timing convergence.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If standard asynchronous FIFO buffers are used for high-bandwidth data transfer between memory and compute logic domains, then data transfer capability is achieved, but area consumption and power consumption increase significantly
Solution Approach 1:
The patent changes the fundamental parameters of FIFO operation by introducing event-driven architecture with producer and consumer event transfer blocks. Instead of traditional synchronous operation with fixed entry counts, the system uses asynchronous event signaling to coordinate data transfer, enabling flexible bandwidth adjustment without proportional area increase. The event blocks dynamically manage transfer timing based on actual data availability and consumption rates.
Solution Approach 2:
The FIFO buffer is segmented into multiple entry points managed by separate producer and consumer event transfer blocks. Each block independently manages its side of the data transfer interface, allowing parallel operation and reducing the critical path length. This segmentation enables the system to achieve high bandwidth by operating multiple data channels simultaneously without requiring a monolithic large buffer structure.
2Productivity
If standard asynchronous FIFO buffers are used for high-bandwidth data transfer, then data transfer capability is achieved, but power consumption increases significantly
Solution Approach 1:
The event transfer blocks operate in a periodic event-driven manner, activating only when data is actually available for production or consumption. This periodic operation pattern eliminates continuous clocking and monitoring of all buffer entries, reducing dynamic power consumption while maintaining high bandwidth capability through efficient event-triggered data transfer pulses.
Solution Approach 2:
The producer and consumer event transfer blocks autonomously manage their respective data transfer operations without requiring external control signals. The blocks self-regulate based on local data availability and consumption readiness, eliminating the need for complex control logic and reducing overall power consumption through simplified operation management.
3Ease of manufacture
If fixed predetermined number of entries is used in FIFO buffer, then implementation is simplified, but efficiency is limited for varying data transfer requirements
Solution Approach 1:
The system transitions from static fixed-size FIFO implementation to dynamic event-driven operation. The producer and consumer event transfer blocks dynamically adjust their operation timing and data transfer quantities based on real-time data availability and consumption patterns. This dynamic behavior enables efficient adaptation to varying data transfer requirements without requiring complex configurable hardware structures.
Data Source
AI summary
A clock domain crossing interface is described. The clock domain crossing interface includes a transmit clock domain and a receive clock domain using a different clock from the transmit clock domain. The clock domain crossing interface also includes a first-in-first-out (FIFO) buffer coupled between the transmit clock domain and the receive clock domain. The FIFO buffer to store ordered transactions sent from the transmit clock domain to the receive clock domain. The clock domain crossing interface further includes a transmit clock domain event transfer block to notify the receive clock domain of a new transaction pushed onto the FIFO buffer in the transmit clock domain. The clock domain crossing interface also includes a receive clock domain event transfer block to notify the transmit clock domain of a new transaction pulled from the FIFO buffer in the receive clock domain.