Asynchronous FIFO With Merging Capability For Low Latency
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
High-speed data communication systems face challenges in minimizing latency due to the inherent delays and signal skew in serial links, particularly in daisy-chained memory architectures like FB-DIMM, which affect memory access performance.
Innovation Solution
A circuitry and method for constructing an asynchronous FIFO with merging capability, utilizing demultiplexers, bit slices, and multiplexers to buffer high-speed input bit streams, align data, and reduce latency while maintaining low power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If high-speed serial links are used for data transmission, then transmission speed is improved, but latency increases due to inherent delays and signal skew
Solution Approach 1:
The patent divides the high-speed serial data stream into multiple parallel lower-speed data streams using demultiplexers. This segmentation allows each parallel stream to be processed independently with less delay, then recombined through multiplexers to achieve low-latency output while maintaining high overall transmission speed.
Solution Approach 2:
The patent transitions from a single-dimensional high-speed serial stream to a multi-dimensional parallel structure by splitting data across multiple channels. This dimensional transformation enables simultaneous processing of multiple data subsets, reducing the time required for complete data transmission and alignment.
2Stability of the object's composition
If FIFO buffers are used to absorb jitter and wander, then signal stability is improved, but latency increases
Solution Approach 1:
The patent segments the FIFO buffering function across multiple parallel channels, allowing each channel to maintain smaller, more efficient buffers. This reduces the overall latency while maintaining signal stability through coordinated processing of all channels.
Solution Approach 2:
The patent combines multiple parallel data streams with their respective buffer outputs through multiplexers, achieving stable signal output with reduced latency. The merging process allows simultaneous data from multiple channels to be consolidated efficiently.
3Manufacturing precision
If demultiplexers and multiplexers are used for data streaming, then data alignment is improved, but power consumption increases
Solution Approach 1:
The patent applies partial action by using simpler demultiplexer and multiplexer circuits that perform only the essential data routing functions without excessive processing. This reduces power consumption while maintaining sufficient data alignment precision for the application.
Solution Approach 2:
The patent changes operational parameters of the demultiplexers and multiplexers, such as clock speeds and buffering depths, to optimize the balance between data alignment precision and power consumption. By adjusting these parameters, the system achieves adequate alignment with lower energy expenditure.
Data Source
AI summary
Where high speed communication between a host and memory devices is carried over serial bit lanes, memory buffers are required for converting buffering the serial bit lanes, and for converting between serial and parallel formats. In addition, jitter, wander, and skew between the bit lanes need to be accommodated. The invention discloses a programmable asynchronous FIFO with the integrated ability to convert blocks of bits from serial to parallel as well as inserting bits from a parallel bus into the serial bit stream. The invention provides very low latency and can be implemented in low power technologies.