Asynchronous FIFO with Multiplexer for Power Domain Crossing
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Solution Overview
Problem
The existing power domain interfaces in integrated circuits face challenges due to large FIFO depths, which require extensive arrays of power-conversion cells, consuming significant area and power, and causing routing difficulties, while also complicating timing closure and increasing power consumption.
Innovation Solution
The implementation of an asynchronous first-in-first-out buffer (AFIFO) with a multiplexer that transfers less than N words onto a fixed interface, allowing the width of the second data bus to be independent of the AFIFO depth, and using read and write pointers to manage data transfers across power domains, reducing the need for low-power cells and minimizing interface size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a large FIFO depth is used to coordinate data exchanges between power domains, then timing requirements are relaxed and data transfer reliability is improved, but the area required for power-conversion cells increases significantly and power consumption increases
Solution Approach 1:
The patent segments the data transfer process by separating the deep FIFO buffer (stored in one power domain) from the shallow interface buffer (at the power domain boundary). This allows the bulk of data storage to occur in a single domain while minimizing the number of power-conversion cells needed at the interface, thus reducing area while maintaining reliability.
Solution Approach 2:
The patent introduces a shallow interface buffer as an intermediary between the deep FIFO and the external interface. This intermediary buffer holds only a small portion of data and works with a reduced set of power-conversion cells, mediating the data transfer process to reduce both area and power consumption while maintaining reliable data exchange.
2Reliability
If a large FIFO depth is used to coordinate data exchanges between power domains, then data transfer reliability is improved, but power consumption increases significantly
Solution Approach 1:
The patent segments the buffer memory into two parts: a deep FIFO buffer located entirely within one power domain (avoiding power conversion overhead) and a shallow interface buffer at the boundary. This segmentation allows most data to be stored without requiring power-conversion cells, significantly reducing interface power consumption while maintaining data transfer reliability.
Solution Approach 2:
The shallow interface buffer acts as an intermediary that minimizes the number of power-conversion cells required. By holding only a small portion of data, it reduces the active area and power consumption at the interface while still providing sufficient buffering for reliable data transfer between power domains.
3Reliability
If a large FIFO depth is used to coordinate data exchanges between power domains, then data transfer reliability is improved, but routing complexity increases due to numerous signals
Solution Approach 1:
The patent segments the data transfer architecture into a deep FIFO in one domain and a shallow interface buffer at the boundary. This reduces the number of signals that need to cross the power domain interface, thereby simplifying routing while maintaining reliable data transfer through the pointer-based coordination mechanism.
4Productivity
If the width of the data bus is increased to match the FIFO depth, then data transfer throughput is improved, but the number of power-conversion cells and interface area increase
Solution Approach 1:
The patent segments the data transfer function into a deep FIFO (for bulk storage) and a shallow interface buffer (for coordinated transfer). This allows the interface to operate with a reduced data bus width that matches the shallow buffer size rather than the deep FIFO size, reducing the number of power-conversion cells and interface area while maintaining acceptable throughput.
Data Source
AI summary
In one aspect of the disclosure, a circuit includes an AFIFO in a first power domain coupled to a first data bus and configured to store up to N data words corresponding to N respective AFIFO outputs. A multiplexer (MUX) in the first power domain selectively coupled to the N AFIFO outputs may transfer, upon receiving a MUX input, less than N words onto a fixed interface. Read logic in a second power domain may send an asynchronous read pointer to the MUX input and may transfer the words output from the fixed interface to a second data bus. Write logic in the first power domain may send asynchronous write pointers to the AFIFO for tracking data writes thereto and to the read logic to determine values of the read pointer.